FPGA implementation of a 10 GS/s variable-length FFT for OFDM-based optical communication systems

Bruno, Julian S.; Almenar, Vicenç; Valls, Javier

doi:10.1016/j.micpro.2018.12.002

Cited by 16 publications

(8 citation statements)

References 24 publications

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“…These have been implemented for image processing [527,1582,1583], pattern recognition [476,1584], real-time processing [671,1477,1585], melanoma cancer detection [510,511,1586,1587], speech recognition [1587,1588] and so forth. Digital signal processing techniques implementations in FPGAs covers FFT [537,[1589][1590][1591][1592][1593], DWT [597,[1594][1595][1596][1597], time-to-digital converters [1598][1599][1600][1601][1602], DCT [580,[1603][1604][1605] and digital filters like FIR filter [56,612,[1606][1607][1608], Kalman filter [620,[1609][1610][1611], median filter [1612,1613], LMS [1614]…”

Section: Discussionmentioning

confidence: 99%

Field Programmable Gate Array Applications—A Scientometric Review

2019

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Field Programmable Gate Array (FPGA) is a general purpose programmable logic device that can be configured by a customer after manufacturing to perform from a simple logic gate operations to complex systems on chip or even artificial intelligence systems. Scientific publications related to FPGA started in 1992 and, up to now, we found more than 70,000 documents in the two leading scientific databases (Scopus and Clarivative Web of Science). These publications show the vast range of applications based on FPGAs, from the new mechanism that enables the magnetic suspension system for the kilogram redefinition, to the Mars rovers’ navigation systems. This paper reviews the top FPGAs’ applications by a scientometric analysis in ScientoPy, covering publications related to FPGAs from 1992 to 2018. Here we found the top 150 applications that we divided into the following categories: digital control, communication interfaces, networking, computer security, cryptography techniques, machine learning, digital signal processing, image and video processing, big data, computer algorithms and other applications. Also, we present an evolution and trend analysis of the related applications.

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Section: Discussionmentioning

confidence: 99%

Field Programmable Gate Array Applications—A Scientometric Review

2019

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“…The CORDIC algorithm provides the precise values of sine and cosine angles in the system. The radix 2 FFT algorithm was implemented on Virtex-7 FPGA [31] based on decimal in frequency algorithm and FFT intellectual property (IP) core in Xilinx software. The design is optimized based on hardware resource utilization, speed, throughput, latency, and accuracy, of computation on an FPGA device.…”

Section: Related Workmentioning

confidence: 99%

Hardware Chip Performance of CORDIC Based OFDM Transceiver for Wireless Communication

Kumar¹,

Kumar²,

Tomar³

2022

Computer Systems Science and Engineering

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The fourth-generation (4G) and fifth-generation (5G) wireless communication systems use the orthogonal frequency division multiplexing (OFDM) modulation techniques and subcarrier allocations. The OFDM modulator and demodulator have inverse fast Fourier transform (IFFT) and fast Fourier transform (FFT) respectively. The biggest challenge in IFFT/FFT processor is the computation of imaginary and real values. CORDIC has been proved one of the best rotation algorithms for logarithmic, trigonometric, and complex calculations. The proposed work focuses on the OFDM transceiver hardware chip implementation, in which 8-point to 1024-point IFFT and FFT are used to compute the operations in transmitter and receiver respectively. The coordinate rotation digital computer (CORDIC) algorithm has read-only memory (ROM)-based architecture to store FFT twiddle factors and their angle generators. The address generation unit is required to fetch the data and write the results into the memory in the appropriate sequence. CORDIC provides low memory, delay, and optimized hardware on the field-programmable gate array (FPGA) in comparison to normal FFT architecture for the OFDM system. The comparative performance of the FFT and CORDIC-FFT based OFDM transceiver chip is estimated using FPGA parameters: slices, flip-flops, lookup table (LUTs), frequency, power, and delay. The design is developed using integrated synthesis environment (ISE) Xilinx version 14.7 software, synthesized using very-high-speed integrated circuit hardware description language (VHDL), and tested on Virtex-5 FPGA.

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“…It also helps to identify the best NoC architecture. FPGAs are reconfigurable and cost-effective devices widely used for implementing high-performance digital communication systems [14,15]. However, less effort is put into leveraging NoC in such architectures in today's systems.…”

Section: Related Workmentioning

confidence: 99%

MIMO-OFDM LTE system based on a parallel IFFT/FFT on NoC-based FPGA

Jallouli

Mazouzi

Diguet³

et al. 2022

Ann. Telecommun.

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The growing demand for wireless devices capable of performing complex communication processes has imposed an urgent need for high-speed communication systems and advanced network processors. This paper proposes a hardware workflow developed for the Long Term Evolution (LTE) communication system. It studies the Multiple-input, multiple-output orthogonal frequency-division multiplexing (MIMO-OFDM) LTE system. Specifically, this work focuses on the implementation of the OFDM block that dominates the execution time in high-speed communication systems. To achieve this goal, we have proposed an NoC-based low-latency OFDM LTE multicore system that leverages Inverse Fast Fourier Transform (IFFT) parallel computation on a variable number of processing cores. The proposed multicore system is implemented on an FPGA platform using the ProNoC tool, an automated rapid prototyping platform. Our obtained results show that LTE OFDM execution time is drastically reduced by increasing the number of processing cores. Nevertheless, the NoC's parameters, such as routing algorithm and topology, have a negligible influence on the overall execution time. The implementation results show up to 24% and 76% execution time reduction for a system having 2 and 16 processing cores compared to conventional LTE OFDM implemented in a single-core, respectively. We have found that a 4×4 Mesh NoC with XY deterministic routing connected to 16 processing tiles computing IFFT task is the most efficient configuration for computing LTE OFDM. This configuration is 4.12 times faster than a conventional system running on a single-core processor.

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FPGA implementation of a 10 GS/s variable-length FFT for OFDM-based optical communication systems

Cited by 16 publications

References 24 publications

Field Programmable Gate Array Applications—A Scientometric Review

Field Programmable Gate Array Applications—A Scientometric Review

Hardware Chip Performance of CORDIC Based OFDM Transceiver for Wireless Communication

MIMO-OFDM LTE system based on a parallel IFFT/FFT on NoC-based FPGA

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