FPGA implementation of addition as a part of the convolution

Jamro, E.; Wiatr, K.

doi:10.1109/dsd.2001.952368

Cited by 12 publications

(11 citation statements)

References 6 publications

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“…The focus of high speed efficient implementation of 2-D convolution therefore shifted to optimization of multiplier units in the PE. LUT based (as in [6] and [7]) and Logarithmic based (as in [5]) multiplier-less schemes were proposed to perform fast multiplication of the incoming pixel stream with the filter coefficients. The conventional LUT based method for multiplication used huge amounts of resources if the filter coefficients were not known beforehand.…”

Section: Introductionmentioning

confidence: 99%

Design of an Area-Efficient Multiplierless Processing Element For Fast Two Dimensional Image Convolution

Deepak

Mahesh

Sluzek

2006

2006 13th IEEE International Conference on Electronics, Circuits and Systems

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Two dimensional (2-D) image convolution is a typical algorithm executed by window-based spatial domain filters, which are in turn used in many applications including intrusion detection. Systolic arrays have been widely used in them by exploiting the hardware parallelism on FPGAs to increase the throughput of the system. These implementations differ mostly in the processing element (PE) architecture employed. We propose a new scheme for the PE in the systolic array architecture which uses a novel area-time efficient lookup table (LUT) based method and reduces the LUT resource usage by almost 50% when compared to the conventional constant coefficient LUT based method.

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Section: Introductionmentioning

confidence: 99%

Design of an Area-Efficient Multiplierless Processing Element For Fast Two Dimensional Image Convolution

Deepak

Mahesh

Sluzek

2006

2006 13th IEEE International Conference on Electronics, Circuits and Systems

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“…The first one (option A) attempts to copy as much as possible from the parents (considering the actual parents structure and disregarding the indices) and then employs a greedy algorithm (simplified version of the GrA implemented in [2]) to route unconnected adders. In the second option (option B), the offspring copies the structure of the first parent and implements changes similar as for the SA, however changes are applied according to the structure of the second parent.…”

Section: Selection -After Fitness Evaluation a New Generationmentioning

confidence: 99%

“…A Greedy Algorithm (GrA) has been proposed by [2]. The GrA determines quickly the network of adders, it is the least computationally demanding algorithm from all techniques considered in this paper.…”

Section: Introductionmentioning

confidence: 99%

“…Nevertheless, the optimisation of the adder block proved to be NP-complete [2], and therefore the Exhaustive Search (ES) can be efficiently implemented only for the number of inputs to the adder block NS8, which requires analysing up to 315 combinations. For example, increasing N to 12 results that 467 775 solutions have to be searched through.…”

Section: Introductionmentioning

confidence: 99%

“…Look-Up- 131. In order to optimise the adder block independently from the multiplier architecture, complicated parameters of inputs to the adder block have been defined [ 2 ] , such as input range (not only input width), input shift, kind of operation (additiodsubtraction), and correlation between inputs.…”

Section: Introductionmentioning

confidence: 99%

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Genetic programming in FPGA implementation of addition as a part of the convolution

Jamro

Wiatr²

Proceedings Euromicro Symposium on Digital Systems Design

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In FPCAs, an addition should be carried out in the standard way employing ripple-carry adders (rather than carry-save adders), which complicates search f o r an optimal adder structure as routing order has a substantial influence on the addition cost. Further, complex parameters of inputs to the adder block have been considered e.g. correlation between inputs. These parameters are specified in different ways for different convoler architectures.

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Optimization of Image‐Processing Algorithms Using FPGAs

Vega

Gómez

et al. 2008

Optimization Techniques for Solving Complex Problems

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FPGA implementation of addition as a part of the convolution

Cited by 12 publications

References 6 publications

Design of an Area-Efficient Multiplierless Processing Element For Fast Two Dimensional Image Convolution

Design of an Area-Efficient Multiplierless Processing Element For Fast Two Dimensional Image Convolution

Genetic programming in FPGA implementation of addition as a part of the convolution

Optimization of Image‐Processing Algorithms Using FPGAs

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