FPGA implementation of AES-based crypto processor

Anwar, Hassan; Daneshtalab, Masoud; Ebrahimi, Masoumeh; Plosila, Juha; Tenhunen, Hannu

doi:10.1109/icecs.2013.6815431

Cited by 18 publications

(7 citation statements)

References 23 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In all our reported results, we employ well-known Eqs. (26) and (27) to calculate the throughput and the throughput to area ratio respectively. For proposed ComI-SpeM, RomI-SpeM, and Com-Mux the number of outputted bits in Eq.…”

Section: Results and Comparisonmentioning

confidence: 99%

“…Moreover, an efficient inter-round and intra-round pipeline design are employed to achieve high throughput. Authors presented a fully pipelined crypto processor in [26] where AES is integrated with a 32-bit general purpose 5-stage pipelined MIPS processor. In [40], authors designed a new VLSI 13 architecture to embed a four stage pipelined S-box in implementation of AES.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

An ultra-high throughput and fully pipelined implementation of AES algorithm on FPGA

Soltani

Sharifian

2015

Microprocessors and Microsystems

View full text Add to dashboard Cite

Section: Results and Comparisonmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

An ultra-high throughput and fully pipelined implementation of AES algorithm on FPGA

Soltani

Sharifian

2015

Microprocessors and Microsystems

View full text Add to dashboard Cite

“…In addition, parallel pipelined architecture achieved a high-speed design with efficient hardware implementation [18]. A 4-stage pipelined S-box and 32-bits general purpose 5-stage pipelined processor are presented advanced Very Large-Scale Integration (VLSI) architectures [19], [20].…”

Section: A Related Workmentioning

confidence: 99%

Energy-Efficient and High-throughput Implementations of Lightweight Block Cipher

2019

IJITEE

View full text Add to dashboard Cite

Security in resource-constrained devices has drawn the great attentions to researchers in recent years. To make secure transmission of critical information in such devices, lightweight cryptography algorithms come in light to large extend. KLEIN has been popular lightweight block cipher used to overcome such issues. In this paper, different architectures of KLEIN block cipher are presented. One of designs enhances the efficiency with regard to the throughput at the expense of a larger area. In order to make such designs, the pipelined registers are placed on different positions in datapath algorithm. The proposed design transforms the data input to protected output with the speed of 2414.13 Mbps for xc5vlx50t-3ff1136 device. In addition, the second design implementation completes either one or more than one round in only one clock and gives energy-efficient and high throughput implementations. Due to this, a trade-off between area and speed can be analyzed for high-speed applications. Moreover, this proposed design shows that with increasing the area of cipher implementation results in more transformation of plaintext into ciphertext. All results are verified and simulated for various families of Xilinx ISE design suite.

show abstract

“…These keys will improve the security levels of data. The normal key's are basically extra persuading and speedier than uneven [2][3][4][5].…”

Section: Fig1: Aes Input/output Parametersmentioning

confidence: 99%

Design of High Speed Advanced Encryption Standard using PPA and PPM

Lakshminarayana¹,

Deshpande²,

Babu³

2019

IJITEE

View full text Add to dashboard Cite

Basically, internet security plays crucial role in past three decades. So in worldwide Advanced Encryption Standard (AES) algorithm is used. AES consists of symmetric block cipher blocks. In this paper we proposed the simplified AES algorithm (S-DES) using parallel prefix adder (PPA) and parallel prefix multiplier (PPM). This parallel prefix adder and parallel prefix multiplier will generate a product formed by multiplying the multiplicand. This algorithm possess specific structure to encrypt and decrypt delicate information and is connected in equipment and programming everywhere throughout the world. It is amazingly hard to programmers to get the genuine information while encoding the AES calculation. The fundamental goal of this algorithm is to build up a model that is executed for correspondence reason, and to test the created model regarding precision reason. The encryption procedure comprises the mix of different traditional methods, for example, substitution, improvement and change encoding strategies. At last the key extension module will comprise the quantity of iterative preparing rounds so as to expand its resistance against unapproved assaults.

show abstract

FPGA implementation of AES-based crypto processor

Cited by 18 publications

References 23 publications

An ultra-high throughput and fully pipelined implementation of AES algorithm on FPGA

An ultra-high throughput and fully pipelined implementation of AES algorithm on FPGA

Energy-Efficient and High-throughput Implementations of Lightweight Block Cipher

Design of High Speed Advanced Encryption Standard using PPA and PPM

Contact Info

Product

Resources

About