FPGA implementation of an 8-bit AES architecture: A rolled and masked S-Box approach

Abstract

As network technology advances, information security issues increase the need for developing low-area and lowpower high performance real-time processing of cryptographic algorithms. In this paper, we present a novel 8-bit architecture for Advanced Encryption Standard (AES) encryption which supports keys of 128-bit in length. The proposed architecture consists of a single round of ShiftRows, ByteSubstitution, MixColumns and AddRoundKey operations through which the data is iterated for ten rounds, which results in substantial reduction in terms of area and power consumption. We have proposed a new architecture for ByteSubstitution and AddRoundKey operations by employing high order masking and a different key expansion algorithm respectively, hence making the proposed architecture less vulnerable to Differential Power Analysis (DPA) and saturation attacks. Moreover, we have also utilized a new architecture for ShiftRows operation for further minimizing the area on chip. The proposed architecture was implemented on Virtex-7 FPGA using two different implementation strategies-Performance Explore and Area Explore using Vivado Design Suite. Using performance explore strategy, the proposed architecture worked at the maximum frequency of 200.32 MHz with a throughput of 160.26 Mbps, whereas, with area explore strategy, the proposed architecture utilized 662 slices, 796 LUTs and 0.303 Watt in power.

Attacking AES-Masking Encryption Device with Correlation Power Analysis

“…SCA is one of attack models that utilizes side informations to obtain the secret key. A cryptographic device is a device that implements cryptographic algorithms on a hardware [6][7][8]. Power analysis is a type of SCA attacks that can reveal confidential information [9].…”

Revealing AES Encryption Device Key on 328P Microcontrollers with Differential Power Analysis

“…In the past, the attack on a cryptographic system is viewed only theoretically. A conventional cryptanalyst generally uses linear, differential, and brute force technique to analyze and obtain the vulnerabilities of an encryption algorithm [1], [2]. The cryptanalyst represents the cryptographic algorithm as a mathematical object.…”

“…By that reason, we see a need of an examination on the vulnerabilities and the points of attacks of the MCU devices which will be used on the IoT devices. However, in fact, when a cryptographic algorithm implemented in hardware will produce high performance, it can be mass produced and low costly [1], [2], [3]. Common forms of cryptographic devices are universal serial bus (USB) tokens, smart card [4], chips, field programmable gate array FPGA [5], [6], and micro-controllers [7].…”