FPGA Implementation of Asynchronous FIFO

Das, Souradeep; Basu, Upasana; Das, Rohit; Saha, Shashwata; Basu, Abhishek

doi:10.1007/978-981-16-7011-4_39

Cited by 3 publications

(1 citation statement)

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“…The main steps of read and write operations are similar: In write operations, write addresses and write Pointers are generated to generate full signals; Read operation, generate read address, read pointer, generate empty signal [8].…”

Section: Write Operate and Read Operatementioning

confidence: 99%

Design of asynchronous FIFO with adjustable depth based on Verilog

Li,

Fu,

Wang

et al. 2023

ACE

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The integrated circuit industry is the basic industry of the digital economy and one of the basic sources of strength to build the new competitive advantage of China's economy in the future. With the development of microelectronic technology, IC technology has becoming more and more integrated, at the same time, the data flow in the different chips are getting complex. To overcome the restriction of the data transmission, FIFO become a way to solve the problem. However, different chips usually work in various clock domains, so the data transmission across clock domains is the key to make the communication between different chips efficient. Meanwhile, the rate of space usage is also a part of chip performance, so the depth of the FIFO is important. Because of the above, an asynchronous FIFO with adjustable depth is designed on Verilog, used Quartus II and Modelsim to draw an RTL diagram of the whole module and simulation.

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Section: Write Operate and Read Operatementioning

confidence: 99%