FPGA implementation of Bayesian network inference for an embedded diagnosis

Zermani, Sara; Dezan, Catherine; Chenini, Hanen; Euler, Reinhardt; Diguet, Jean-Philippe

doi:10.1109/icphm.2015.7245057

Cited by 29 publications

(23 citation statements)

References 18 publications

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“…These values are then translated into coupling term J ij and bias term h i by following similar principles as in deriving Eqs. (5) and (6). The derivation for J ij and h i for an n-node Bayesian network is provided by Faria et al 19 The dimensionless terms J ij and h i are then translated to corresponding Oersted fields to each p-bit by a relation: www.nature.com/scientificreports/ The coupling and bias component of H i can be realized through the coupling resistance R weight and R bias respectively with a mapping principle as described in Eqs.…”

Section: Simulation Of a Four Node Bayesian Networkmentioning

confidence: 99%

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Hardware implementation of Bayesian network building blocks with stochastic spintronic devices

Debashis

Ostwal

Faria

et al. 2020

Sci Rep

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Bayesian networks are powerful statistical models to understand causal relationships in real-world probabilistic problems such as diagnosis, forecasting, computer vision, etc. For systems that involve complex causal dependencies among many variables, the complexity of the associated Bayesian networks become computationally intractable. As a result, direct hardware implementation of these networks is one promising approach to reducing power consumption and execution time. However, the few hardware implementations of Bayesian networks presented in literature rely on deterministic CMOS devices that are not efficient in representing the stochastic variables in a Bayesian network that encode the probability of occurrence of the associated event. This work presents an experimental demonstration of a Bayesian network building block implemented with inherently stochastic spintronic devices based on the natural physics of nanomagnets. These devices are based on nanomagnets with perpendicular magnetic anisotropy, initialized to their hard axes by the spin orbit torque from a heavy metal under-layer utilizing the giant spin Hall effect, enabling stochastic behavior. We construct an electrically interconnected network of two stochastic devices and manipulate the correlations between their states by changing connection weights and biases. By mapping given conditional probability tables to the circuit hardware, we demonstrate that any two node Bayesian networks can be implemented by our stochastic network. We then present the stochastic simulation of an example case of a four node Bayesian network using our proposed device, with parameters taken from the experiment. We view this work as a first step towards the large scale hardware implementation of Bayesian networks.

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Section: Simulation Of a Four Node Bayesian Networkmentioning

confidence: 99%

“…Several hardware implementations of BNs have been proposed based on CMOS hardware. For example, Zermani et al 5 demonstrated FPGA based BN implementation utilizing suitable architectural design and memory allocation schemes. Cai et al 6 demonstrated another FPGA based architectural design along with a suitable pseudo random number generator.…”

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confidence: 99%

Hardware implementation of Bayesian network building blocks with stochastic spintronic devices

Debashis

Ostwal

Faria

et al. 2020

Sci Rep

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“…To implement Decision Making based probabilistic (Bayesian) network onboard, some research has shown encouraging results with FPGA based reconfigurable hardware [19] [18] [15] [16]. In [9], the authors proposed an FPGA implementation based on a BN representation, that allows to continuously monitor the embedded system under time and resource constraints. For this purpose, they proposed off-line framework integrating a high level synthesis tool to generate the hardware version.…”

Section: Previous Related Workmentioning

confidence: 99%

“…In this work, we propose an extended framework [9] that can generate an FPGA bitstream from the BN specification. In fact, the hardware implementation of BN inference on synthesizable hardware as FPGAs can be divided into two main phases:…”

Section: B Hw/sw Implementations Of the Proposed Mission Decision Mamentioning

confidence: 99%

Embedded Mission Decision-Making based on Dynamic Decision Networks in SoPC Platform

Chenini¹

2019

IJACSA

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This paper tackles a Bayesian Decision Making approach for unmanned aerial vehicle (UAV) mission that allows UAV to quickly react to unexpected events under dynamic environments. From online observations and the mission statement, the proposed approach is designed by means of Dynamic Bayesian Networks (DBN) arising from the safety or performance failures analysis. After proposing a DBN model, a probabilistic approach based on Multiple-Criteria Decision-Making (MCDM) is then applied to find the best configuration reaching a balance between performance and energy consumption, thus decide which tasks will be implemented as SW and which as HW execution units, regarding the mission requirement. The proposal UAV mission decision-making is three-pronged, providing: (1) real time image pre-processing of sensor observations; (2) temporal and probabilistic approach based on Bayesian Networks to continuously update the mission plan during the flight; and (3) low-power hardware and software implementations for online and real time embedded Decision Making using Xilinx System on Programmable Chip (SoPC) platform. The proposed approach is then validated with a practical case UAV mission planning using the proposed dynamic decision-maker implemented on embedded system based on a hybrid device.

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“…BN's are widely used to understand causal relationships in real world problems such as forecasting, diagnosis, automated vision, manufacturing control and so on 12 . For deep and complicated networks where each child node has many parent nodes, the computation of the joint probability becomes impractical 13 and different hardware implementations of BN's have been proposed [14][15][16][17][18][19][20][21][22] .In this letter we present a systematic approach for translating a BN into an electronic circuit such that the stochastic node voltages mimic the real world variables whose correlations can be obtained from electrical measurements on the corresponding circuit nodes. The proposed electronic circuit and the hardware building blocks are based on present day Magnetoresistive Random Access Memory (MRAM) technology whose MTJs are built out of thermally unstable nanomagnets 5 (Stochastic MRAM), obviating the need for the development of a new device.As a benchmark example, consider a BN (Fig.…”

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confidence: 99%

Implementing Bayesian networks with embedded stochastic MRAM

2018

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Magnetic tunnel junctions (MTJ's) with low barrier magnets have been used to implement random number generators (RNG's) and it has recently been shown that such an MTJ connected to the drain of a conventional transistor provides a three-terminal tunable RNG or a p-bit. In this letter we show how this p-bit can be used to build a p-circuit that emulates a Bayesian network (BN), such that the correlations in real world variables can be obtained from electrical measurements on the corresponding circuit nodes. The p-circuit design proceeds in two steps: the BN is first translated into a behavioral model, called Probabilistic Spin Logic (PSL), defined by dimensionless biasing (h) and interconnection (J) coefficients, which are then translated into electronic circuit elements. As a benchmark example, we mimic a family tree of three generations and show that the genetic relatedness calculated from a SPICE-compatible circuit simulator matches well-known results.

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FPGA implementation of Bayesian network inference for an embedded diagnosis

Cited by 29 publications

References 18 publications

Hardware implementation of Bayesian network building blocks with stochastic spintronic devices

Hardware implementation of Bayesian network building blocks with stochastic spintronic devices

Embedded Mission Decision-Making based on Dynamic Decision Networks in SoPC Platform

Implementing Bayesian networks with embedded stochastic MRAM

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