FPGA implementation of binary coded decimal digit adders and multipliers

Al-Khaleel, Osama; Tulic, Nuh H.; Mhaidat, Khaldoon

doi:10.1109/isma.2012.6215199

Cited by 12 publications

(24 citation statements)

References 5 publications

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“…Here two CAD techniques for leakage power are proposed which reduce leakage power without imposing any cost and having no effect on area, efficiency, cost for fabricating IC and its speed also. Khaleel et al [3] have focused on making an efficient binary coded decimal digit adder. Where the author proposed two designs using VHDL and Xilinx ISE 10.1 targeting Xilinx virtex-5 XC5VLX30-3 FPGA.…”

Section: Literature Surveymentioning

confidence: 99%

Matlab Interface For Power And Timing Analysis Of Digital Circuits

Verma¹,

Abhishek²,

Chauhan³

et al. 2017

GJET

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Due to advent in CMOS technology, it has become possible now to put millions of transistors on a single chip of silicon. This has drastically increased the performance of the device and it can do much faster operations. But on the other side, putting more transistors on a silicon chip triggering the problem of increased power consumption. So, it becomes a bottleneck for the designer to choose in between performance and power consumption. Particularly, for reconfigurable hardware like FPGAs the situation is worst and demands concern. So, this paper presents some optimization techniques that are applied on FPGAs at different levels of abstraction. Some benchmark circuits like ALU, Register, Counter and RAM are used for experimental measurements to validate the results. After simulation and power analysis of benchmark circuits at different frequencies, a power aware utility software is developed that performs optimization of power keeping performance in consideration at a given frequency for the selected FPGA. The circuits have been implemented using VHDL as the hardware description language and simulation is carried out using Xilinx ISE 14.1 by targeting Virtex-4, 5 and Artix-7 FPGA.

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Section: Literature Surveymentioning

confidence: 99%

Matlab Interface For Power And Timing Analysis Of Digital Circuits

Verma¹,

Abhishek²,

Chauhan³

et al. 2017

GJET

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“…One reason is that the obvious solutions for BDM-based PPG fail to be advantageous at least in one of the figures of merit in performance evaluation. For example, the straightforward fully truth table-based solution [2], although conceptually simple, tends to require tedious design effort, results in circuits that consume very large area, and/or dissipate high power in contrast to sequential designs. Given the high price of area intensive VLSI products in the past decades, such precautions has been serious enough to discourage the design engineers from even picturing in mind the VLSI layout of a practical 16×16-digit BCD multiplier with 256 BDM cells, where 16 is the default size of decimal operands in the IEEE 754-2008 standard for decimal floating point arithmetic [13].…”

Section: Brief Review Of Bcd Digit Multipliersmentioning

confidence: 99%

“…Table Approach The last design, which we hereby point out to, is in fact the most straightforward solution, with direct derivation of the relevant Boolean expressions with no intermediate binary product. An FPGA realization of such approach has been recently reported in [2], where as is pointed out therein, the corresponding truth table has 156 "Don't care" entries (in other words, 100 valid entries out of 256). This has greatly simplified the relevant Boolean equations.…”

Section: Iterative Array Approachmentioning

confidence: 99%

“…On the same grounds, a direct approach with no binary product interface has been recently undertaken [2], where a BDM is designed via fully truth table-based logic and realized on FPGA with high-level programming (i.e., directly providing the corresponding Boolean expressions to the FPGA tool for automatic realization). However, we use low-level FPGA programming for the same task to get at a faster BDM.…”

Section: Introductionmentioning

confidence: 99%

“…3, we revisit, with some corrections and improvements, two of the previous designs. Subsequently, two new low-cost designs and our new ASIC and FPGA realization of the work of [2] are discussed in Sect. 4.…”

Section: Introductionmentioning

confidence: 99%

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Efficient ASIC and FPGA Implementation of Binary-Coded Decimal Digit Multipliers

Gorgin

Jaberipur

Asl

2014

Circuits Syst Signal Process

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Partial product generation (PPG), in radix-10 multiplication hardware, is often done through selection of pre-computed decimal multiples of the multiplicand. However, ASIC and FPGA realization of classical PPG via digit-by-digit multiplication has recently attracted some researchers. For example, a sequential multiplier, squarer, divider, FPGA parallel multiplier, and array multiplier are all based on a specific binary-coded decimal (BCD) digit multiplier (BDM). Most BDMs, as we have encountered, compute the binary product of two 1-digit BCD operands, and convert it to 2-digit BCD product. We provide our own version of two of these works with some adjustments and improvements, and offer two new low-cost BDMs in this category. However, a recent FPGA BDM uses straightforward truth table approach from scratch and skips binary product generation. We redesign the latter via low-level FPGA programming, and also provide its ASIC realization. We synthesize all the studied and new designs on ASIC and FPGA platforms, exhaustively check them for correctness, and compare their performance, to show that our two new designs, and the ASIC and new FPGA realizations of the aforementioned fully truth table-based design, outperform the previous ones in terms of one or more figures of merit.

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