FPGA Implementation of FIR Nyquist Filters

Abstract

In this paper, Field-Programmable Gate Array (FPGA) implementations of FIR Nyquist filters are presented. Array processor realizations for FIR Nyquist filter are considered and analyzed, namely the direct, transposed, hybrid, and folded forms. Design examples are considered for low-delay and linear-phase FIR Nyquist filters. The filters are then realized as a combination of the appropriate structures and delay elements. Register Transfer Level (RTL) simulations, gate-level simulations and FPGA physical synthesis are performed on both design examples.