FPGA implementation of full-search vector quantization based on partial distance search

Hwang, Wen-Jyi; Wei, Wen-Kang; Yeh, Yao-Jung

doi:10.1016/j.micpro.2006.02.014

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Cited by 4 publications

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“…The applications considered in our experiments are the vector quantization (VQ) for signal compression [4]. Although some VLSI architectures [1,7,11] have been proposed for VQ applications, these architectures are used only for VQ encoding. The proposed architecture is used for the training of VQ codewords.…”

Section: Introductionmentioning

confidence: 99%

Efficient K-Means VLSI Architecture for Vector Quantization

Hwang

Hsu

et al. 2009

Image Analysis

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Abstract.A novel hardware architecture for k-means clustering is presented in this paper. Our architecture is fully pipelined for both the partitioning and centroid computation operations so that multiple training vectors can be concurrently processed. The proposed architecture is used as a hardware accelerator for a softcore NIOS CPU implemented on a FPGA device for physical performance measurement. Numerical results reveal that our design is an effective solution with low area cost and high computation performance for k-means design.

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