FPGA Implementation of High-Efficiency ECC Point Multiplication Circuit

Abstract

The authentication of Internet of Things (IoT) devices based on the Physical Unclonable Function (PUF) is widely adopted in the information security domain. However, the leakage of PUF responses in an authentication system reduces its privacy and security. To improve its security, we can utilize the Elliptic Curve Cryptography (ECC) algorithm with different key lengths to encrypt the PUF response arbitrarily. Point multiplication is the most time-consuming operation in ECC because of its complex calculation process, which seriously affects the efficiency of the PUF response encryption. In order to solve this problem, a point multiplier based on binary field with reconfigurable key lengths of 233, 283, 409 and 571 is designed in this paper. In our method, by reusing the underlying computing units, the resources needed for point multiplication are effectively reduced. What it is more innovative is that double point multiplication operations with a key length of less than 283 bits can be performed simultaneously in the elaborate designed point multiplication circuit, which can effectively speed up the encryption process of ECC. The circuit is implemented on Xilinx Virtex-6 FPGA. The experiment results show the single point multiplication times of 233, 283, 409 and 571 key lengths are 19.33, 22.36, 41.36 and 56.5 μs, respectively, under the clock frequency of 135 MHz. In addition, it only needs 19.33 μs to perform two-point multiplication operations when the key length is 233 bits at the same time. When the key length is 283 bits, the point multiplication operation can be performed twice in 22.36 μs.

Power/Area-Efficient ECC Processor Implementation for Resource-Constrained Devices

“…As compared to [11,17] our design saves 41.69% and 63.9% of FPGA slices and shows 30% and 35% efficiency improvement, respectively. Moreover, our design implemented on Virtex 5 and Virtex 6 outperforms [10,12,33] in terms of efficiency.…”

“…Compared to [15,21], it saves 3045 slices and 4934 slices, respectively. Compared to [10,12,33], our design implemented on Virtex 5 shows the higher efficiency.…”

High speed elliptic curve cryptography architecture for NIST recommended Galois field

“…They have attained throughput over the area and GF (2233) on XilinxVirtex-7, Virtex-6, and Virtex-5 FPGA platforms. Zhao et al [17] proposed a point multiplier with a binary field and a reconfigurable secure key with prime field sizes of p-233, p-283, p-409, and p-571.…”

FPGA Implementation of Elliptic-Curve Point Multiplication Over GF(2233) Using Booth Polynomial Multiplier for Area-Sensitive Applications

“…Radio-frequency identification networks (RFID) [9], [10], [11], internet-of-things (IoTs) [12], [13], [14], [15] and wireless sensor nodes (WSNs) [16] are typical examples of area-constrained cryptographic applications that demand low complexity H/W realization of the ECC's PM computation. Instead of these applications, other related applications are error correction codes [17], digital signal processors [18], network servers [19], etc.…”