FPGA Implementation of Pairings Using Residue Number System and Lazy Reduction

Abstract

International audienc

Core Based Architecture to Speed Up Optimal Ate Pairing on FPGA Platform

“…For executing extension field operations we always invoke our only multiplier for generating reduced result for each F p -multiplication. To speed up extension field arithmetic sometimes a lazy reduction technique is used [6]. However, instead of lazy reduction, our new multiplier executes multiple simultaneous F p -multiplications on pipelined datapath which ultimately speed up the overall pairing computation.…”

“…The step-by-step computation of the doubling step and f 2 is provided in Algorithm 5 of A.2. The formula of doubling step is followed from the state of the art existing pairing implementations [2,6,7]. We made rearrangements of the computations for making it suitable for our design.…”

“…However, due to the dual adder/subtractor units these stall cycles are small compared to overall execution cycles. The formula for computing this step in Projective coordinates is provided in [2,6,7]. Algorithm 6 in A.2 provides the same with little rearrangements of operations to fit our current scheduling.…”

“…In contrasts to pipelined design of [6] the current design uses MSB first method. Due to the low Hamming weight of |z| the multiplications cost is vary low compared to the costs of squarings, and the current pipeline is suitable to execute one individual non-linear operation in F p 12 .…”

“…A dedicated inversion unit is also incorporated into the design for reducing further cycle count. In total, the final design achieves 32% speedup from the existing premier design [6] for computing optimal-ate pairing.…”