Fpga Implementation of Priority-Arbiter Based Router Design for Noc Systems

Abstract

An efficient Priority-Arbiter based Router is designed along with 2X2 and 3X3 mesh topology-based NOC architecture are designed. The Priority-Arbiter based Router design includes Input registers, Priority arbiter, and XY-Routing algorithm. The Priority-Arbiter based Router and NOC 2X2 and 3X3 Router designs are synthesized and implemented using Xilinx ISE Tool and simulated using Modelsim6.5f. The implementation is done by Artix-7 FPGA device, and the physically debugging of the NOC 2X2 Router design is verified using Chipscope pro tool. The performance results are analyzed in terms of the Area (Slices, LUT's), Timing period, and Maximum operating frequency. The comparison of the Priority-Arbiter based Router is made concerning previous similar architecture with improvements.