FPGA implementation of spatial filtering techniques for 2D images

Sadangi, Sushant; Baraha, Satyakam; Satpathy, Darshan Kumar; Biswal, Pradyut Kumar

doi:10.1109/rteict.2017.8256791

Cited by 12 publications

(4 citation statements)

References 3 publications

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“…The success of the WMF in conserving picture detail largely relies on the weighting factors of the input image. In practice, finding adequate weighting factors for this filter is challenging, and this filter demands a long computing time when the weights are considerable [15][16][17][18].…”

Section: Weighted Median Filtermentioning

confidence: 99%

A new method for designing an efficient switching median filter using VLSI architecture to remove salt and pepper noise

AbdElminaam

Rafiq²,

Muthusamy³

et al. 2022

Journal of Computing and Communication

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Any imaging system's images have dynamic intensity value variations, rapid light shifts, and poor contrast. Such visuals are empty of useful information and difficult to comprehend visually. Filtering methods to eliminate noise, improve contrast, and detect edges are used to retrieve secondary information from such photographs. Median filtering is one of the nonlinear ways that remove the range of isolated noise like salt and pepper noise while preserving the edge information of the image. However, median filtering fails to remove the noise when the image is affected by too strong impulsive noise. The switching median filtering technique can be used to eliminate high-intensity impulse noise. This research presents a VLSI design for a novel switching-based median filter to reduce high-density salt and pepper noise in digital images. The absolute difference between the center pixel and the array median obtained from a 3 x 3 sliding window is compared to a predefined threshold value to determine whether a pixel is noisy or not. During the filtering stage, the noisy pixels in the 3 x 3 filtering window are replaced by the median of noise-free pixels. If a pixel value is damaged, it is replaced with the median of the following window. The true pixel intensity value is kept if the pixel is not destroyed. We can tell if a pixel is corrupted or not by using a threshold detector. We may either add salt and pepper noise to an image directly or create it ourselves. This is a step in the image preparation process. The normal image is uploaded and converted it to a salt and pepper noise image using MATLAB's built-in capabilities. We used three tools in our project. We used MATLAB to preprocess the picture and plot data to reconstruct the original image, then ModelSim to produce the median filter, and XILINX to compare the existing bubble sort to the recommended threecell sorter. The proposed technique outperforms standard median-based filters in simulations and is particularly effective in circumstances where pictures are badly damaged.

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Section: Weighted Median Filtermentioning

confidence: 99%

A new method for designing an efficient switching median filter using VLSI architecture to remove salt and pepper noise

AbdElminaam

Rafiq²,

Muthusamy³

et al. 2022

Journal of Computing and Communication

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“…The existing multipliers partial products require additional area in the architecture. So, the focus was on speeding up [10] the process with partial product reduction in the architecture with minimum power and area. Shen and Chen [11] designed a low power multiplier by decreasing the switching activities of the partial product using the Booth algorithm.…”

Section: A General Architecture Of Macmentioning

confidence: 99%

A Novel Approach to Develop Low Power MACs for 2D Image Filtering

Samanth

Nayak

2021

IEEE Access

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In emerging technologies, a vital role is played by ASIC designs in processor operations. There is a necessity to develop such a processor composed of low power blocks. This paper discusses the design exploration of the fixed-point multiply-accumulate unit to achieve high-speed and low power consumption. A 2D image convolution process is developed by stacking and combining several MAC blocks. The developed MAC comprises a sequential multiplier, controller, and optimized adder units. The entering image pixels and kernel pixels are checked for similarity and accordingly isolated by the controller unit, thereby saving power by eliminating the redundant multiplications. A novel idea of reducing the additions in image filtering operations is incorporated in the design. The performance of the proposed MAC showed a 28% power reduction compared to the conventional approaches.

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“…39 As images require large data set to represent them, designing an image processing in software is flexible but at the cost of computationally efficient. Researchers 40,41 have analyzed image processing algorithms both in Matlab and HDL and concluded performance is similar. Dedicated hardware can do the image processing faster and allows for further optimization of the design.…”

Section: Hardware Implementation Of Image Processing Algorithmsmentioning

confidence: 99%

“…It is used for 2D filtering by superimposing a fixed window onto a target signal and researchers explored efficient computation techniques. 40,41,51 Parallel computing in FPGA 80 was used to implement a multi-window buffering scheme for 2D convolution and achieved a better bus memory width. The convolution operation is primary in CNN and a power-efficient convolution core is implemented with a fixed-point multiplier for CNN.…”

Section: Hardware Implementation Of Image Processing Algorithmsmentioning

confidence: 99%

A study on VLSI implementation of image enhancement techniques

Aklak

Pugazhenthi²,

Alex

2021

Concurrency and Computation

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In real-time, the images captured are not always appreciable for visual perception.The quality of the image relies on the illumination condition. Contrast enhancement is required to improve the visual quality of the image. In this article, the image enhancement techniques that are adaptable for real-time images are studied. Further, an investigation is done on implementing the image processing algorithms in very large-scale integration (VLSI) hardware. As the image data are comparatively larger, the computational complexity and the memory requirement are more. From the study, the need for efficient computation of such image processing algorithms is realized. The efficient computation of image processing algorithms on hardware platforms, in particular on field programmable gate array (FPGA), is reviewed. As an experiment, the gamma-transformation technique used for image enhancement is realized. Initially, the prototype is modeled using MATLAB, and then it is implemented using an FPGA. K E Y W O R D Sfield programmable gate array, floating point multiplier, image enhancement INTRODUCTIONIn the modern digital world, all multimedia transactions require good-quality images. The visibility of an image depends on the illuminance and reflectance of the scene in the real world. The brightness of a point in an image is non-linear to the brightness of the same point in the real world.Generally, lighting condition determines the quality of an image. The images taken under poor lighting conditions may cause discomfort while viewing images.The image acquired can be degraded due to various reasons such as sensor level malfunction, low visibility, excessive exposure, foggy conditions, and so on. 1 To overcome the degradation, pre-processing is required to enhance the image. Image enhancement is the process of adjusting digital images so that the results are more suitable for display or further processing. It includes processes like deblurring, noise removal, filtering, and so on.Not all images will require the same image enhancement technique because there may be over-exposed regions in outdoor images that will need different treatment compared to indoor images. In literature, there are many algorithms proposed for image enhancement. The technique of being applied for enhancement depends on the input quality of the image. The quality needs to be assessed before applying any approach for a better perception of the image. A real-time implementation of image enhancement is hard to design using software because a large data set is required to represent an image. Since field programmable gate arrays (FPGAs) could exploit the spatial parallelism in image enhancement algorithms they are widely used for hardware implementation.Realizing the design on FPGAs, offer a compromise between the flexibility of general-purpose processors and the hardware-based speed of an integrated-circuit design. 2 Also, the programmable property of FPGA makes them a good choice for image processing applications, as the processing of the number of images also...

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FPGA implementation of spatial filtering techniques for 2D images

Cited by 12 publications

References 3 publications

A new method for designing an efficient switching median filter using VLSI architecture to remove salt and pepper noise

A new method for designing an efficient switching median filter using VLSI architecture to remove salt and pepper noise

A Novel Approach to Develop Low Power MACs for 2D Image Filtering

A study on VLSI implementation of image enhancement techniques

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