FPGA Implementation of Vedic Squarer for Communication Systems

Abstract

The squarer or squaring circuit is extensively used in communication systems as a mathematical function with applications of frequency doublers, finite impulse response (FIR) filters, peak amplitude detectors, digital processors and analog multipliers, etc. and especially for square law detection circuits. Vedic multipliers are popular mainly for it’s simplicity in the literature of digital multipliers. Recently proposed 2-bit square calculator or self-multiplier already took the attraction of the researchers. In this paper, two bits squarer or self-multiplier or square calculator has been successfully coded using VHDL, verified in Xilinx tool and finally implemented in popular FPGA Spartan kit.

Area & power modeling for different tree topologies of parallel prefix adders

“…Y A Durrani et al in [14] has proposed architectural level macro-modeling for power estimation of IP components using the statistical information of inputs and outputs. Likewise, recent work by A Khan et al in [15] successfully demonstrates the VHDL coding and implementation of square calculator on popular Spartan series FPGA device. Another latest work by S Sen et al [16] proposes an efficient analytical power estimation models to estimate switching loss or power loss in Power MOSFET device.…”