FPGA Implementations of the Round Two SHA-3 Candidates

Baldwin, Brian; Byrne, Andrew; Lü, Liang; Hamilton, Mark; Hanley, Neil; O’Neill, Máire; Marnane, William P.

doi:10.1109/fpl.2010.84

Cited by 69 publications

(29 citation statements)

References 6 publications

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“…The previous results most relevant to the subject of this paper belong to the category of High-Speed Implementations in FPGAs. The most comprehensive results belonging to this category have been reported in [5] [8][12] [13]. All these papers include results for all 14 Round 2 candidates.…”

Section: Previous Workmentioning

confidence: 99%

Throughput vs. Area Trade-offs in High-Speed Architectures of Five Round 3 SHA-3 Candidates Implemented Using Xilinx and Altera FPGAs

Homsirikamol

Rogawski

Gaj

2011

Cryptographic Hardware and Embedded Systems – CHES 2011

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Abstract. In this paper we present a comprehensive comparison of all Round 3 SHA-3 candidates and the current standard SHA-2 from the point of view of hardware performance in modern FPGAs. Each algorithm is implemented using multiple architectures based on the concepts of folding, unrolling, and pipelining. Trade-offs between speed and area are investigated, and the best architecture from the point of view of the throughput to area ratio is identified. Finally, all algorithms are ranked based on their overall performance, and the characteristic features of each algorithm important from the point of view of its implementation in hardware are identified.

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Section: Previous Workmentioning

confidence: 99%

Throughput vs. Area Trade-offs in High-Speed Architectures of Five Round 3 SHA-3 Candidates Implemented Using Xilinx and Altera FPGAs

Homsirikamol

Rogawski

Gaj

2011

Cryptographic Hardware and Embedded Systems – CHES 2011

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“…There exist several Keccak implementations where most of them have been designed for FPGAs. Highspeed implementations have been reported by J. Strömbergson [39], B. Baldwin et al [3], E. Homsirikamol et al [22], K. Kobayashi et al [31], F. Gürkaynak et al [20], and K. Gaj et al [16,17]. Low-area FPGA designs have been presented by S. Kerckhof et al [29], J.-P. Kaps et al [26], and B. Jungk and J. Apfelbeck [25].…”

Section: Hash Functions For Rfidmentioning

confidence: 97%

Pushing the Limits of SHA-3 Hardware Implementations to Fit on RFID

Pessl

Hutter

2013

Cryptographic Hardware and Embedded Systems - CHES 2013

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Abstract. There exists a broad range of RFID protocols in literature that propose hash functions as cryptographic primitives. Since Keccak has been selected as the winner of the NIST SHA-3 competition in 2012, there is the question of how far we can push the limits of Keccak to fulfill the stringent requirements of passive low-cost RFID. In this paper, we address this question by presenting a hardware implementation of Keccak that aims for lowest power and lowest area. Our smallest (fullstate) design requires only 2 927 GEs (for designs with external memory available) and 5 522 GEs (total size including memory). It has a power consumption of 12.5 µW at 1 MHz on a low leakage 130 nm CMOS process technology. As a result, we provide a design that needs 40 % less resources than related work. Our design is even smaller than the smallest SHA-1 and SHA-2 implementations.

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“…Regarding the hardware implementations of Skein, the works presented in literature can be classified in two main categories. The first category includes the works that perform comparative studies among the candidates of NIST's hash competition [24][25][26][27][28][29][30][31][32][33][34][35][36][37][38][39][40][41]. The main goal of these works is not to develop sophisticated architectures but to study the performance of these algorithms when they are implemented in hardware.…”

Section: Introductionmentioning

confidence: 99%