FPGA Investigation on Error-Floor Performance of a Concatenated Staircase and Hamming Code for 400G-ZR Forward Error Correction

Towards FPGA Emulation of Fiber-Optic Channels for Deep-BER Evaluation of DSP Implementations

“…However, as these systems become more complex, the effort spent on test and characterization of the implementation can become prohibitively large [1]. For designs in which deep bit-error rate (BER) results are needed, e.g., forward error correction (FEC), the time spent on testing will increase further, since simulations of up to 10 16 transmitted bits are not uncommon [2]. An additional methodological challenge is that algorithms implemented in hardware description languages (HDLs) likely differ from ideal floating-point MATLAB or C implementations, since the mapping of algorithms to fixed-point, sequential hardware creates implementation artifacts that are not only hard to anticipate, but also hard to model in hardware-agnostic environments like MATLAB [3].…”

“…Although accurate, this method is very slow. To speed up simulation and enable deep-BER analysis, fieldprogrammable gate arrays (FPGAs) have become indispensable, especially for FECs [2]. The additive white Gaussian noise (AWGN) source traditionally in focus is clearly necessary when modelling a realistic channel [4].…”

Performance of chip-scale optical frequency comb generators in coherent WDM communications

“…As a reference, the plot indicates the minimum OSNR required for transmission of a net data rate of 400 Gbit/s and 600 Gbit/s per WDM channel, using 16QAM and 64QAM as a modulation format, respectively. In both cases, advanced forward-error correction schemes with 11 % overhead and BER thresholds of 2 1.2 10 −  [26] are assumed, requiring a symbol rate of 56 GBd to provide the specified net data rates.…”

FPGA implementation of distribution matching and dematching

“…We predicted its performance at very low bit error rates (BERs) analytically and by simulations in [7]. However, very low BERs have never been measured for any DM scheme, while FEC was evaluated at BER at less than 10 -10 via a field programmable gate array (FPGA) implementation [12].…”