2007
DOI: 10.1109/acssc.2007.4487581
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FPGA Realization of Peak-to-Average Power Ratio Reduction Techniques for OFDM Wireless Systems

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Cited by 2 publications
(2 citation statements)
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“…The field programmable gate array (FPGA) has many advantages in digital signal processing, including high density integration, parallel operation mechanisms, high speed processing, and flexible implementation. It has become one of the main choices for implementing PAPR reduction algorithms in real systems [18,19]. In this section, we illustrate how to implement the proposed TTPS-based Tone Reservation algorithm on FPGA chips.…”
Section: Fpga Implementationmentioning
confidence: 99%
“…The field programmable gate array (FPGA) has many advantages in digital signal processing, including high density integration, parallel operation mechanisms, high speed processing, and flexible implementation. It has become one of the main choices for implementing PAPR reduction algorithms in real systems [18,19]. In this section, we illustrate how to implement the proposed TTPS-based Tone Reservation algorithm on FPGA chips.…”
Section: Fpga Implementationmentioning
confidence: 99%
“…As results, the transmitter with high dynamic ranges should be used to overcome such deficiency. Hence, it has turned the researchers' attention toward how to optimize and propose solution at the expense of the computational complexity, the bit error rate (BER) degradation, or the side information transmission process (SI) that decreases the spectral efficiency, such as amplitude clipping, selective mapping (SLM), partial transmit sequence (PTS), coding based schemes, shifted phase sequence techniques, transformation based techniques and tone based schemes [15][16][17][18]. Generally, the predicted PAPR in the OFDM signal can be easily written as: (2) Here, is the transmitted OFDM symbol that is generated by modulating a data block of symbols;…”
Section: Peak-to-average Power Ratiomentioning
confidence: 99%