FPGA resource and timing estimation from Matlab execution traces

Abstract

We present a simulation-based technique to estimate area and latency of an FPGA implementation of a Matlab specification. During simulation of the Matlab model, a trace is generated that can be used for multiple estimations. For estimation the user provides some design constraints such as the rate and bit width of data streams. In our experience the runtime of the estimator is approximately only 1/10 of the simulation time, which is typically fast enough to generate dozens of estimates within a few hours and to build cost-performance trade-off curves for a particular algorithm and input data. In addition, the estimator reports on the scheduling and resource binding used for estimation. This information can be utilized not only to assess the estimation quality, but also as first starting point for the final implementation.

Accurate area estimation model for FPGA based Implementation

“…Area estimation for different input description languages is widely studied (C [1,[4][5], SA-C [6], SystemC [7], MATLAB [8], Simulink [9], VHDL [10] …etc). Most of the published work performs a transformation step to express the input description into an Intermediate Representation (IR) such as Trimaran IR [4], Control Data Flow Graph (CDFG) [5], and VHDL AST [10], and then, apply the estimation process on the intermediate format.…”

“…Regarding the target technology, current approaches target either ASIC-based designs [11][12] or FPGA-based designs [4][5][6][7][8][9][10][14][15][16][17][18][19][20].FPGA-based area estimators either incorporate a physical model for the FPGA and estimate the area by performing actual mapping [14],by using modelling equations of the FPGA functional resources [4][5][6][7][8][9][10][15][16][17], or by building a large database for all possible resources configurations [18][19].As the routing of signals between resources can consume extra area, this area is difficult to determine prior to placement and routing. Fortunately, this routing area does not usually constitute a very large fraction of the overall area for the small and medium designs [6].…”

The COMPLEX reference framework for HW/SW co-design and power management supporting platform-based design-space exploration

“…Trace-based techniques: Trace-based techniques can also be used to provide hardware performance analysis [25]. In this approach, a trace is generated during source-code execution (simulation-based approach).…”

A Review of FPGA-based design methodologies for efficient hardware Area estimation

“…For the area estimation, some techniques are tailored for certain partitioning schemes [4,5]. Area estimation for different input description languages is widely studied(C [3,6,7],SA-C [8],SYSTEM C [9] ,MATLAB [10] SIMULINK [11],VHDL [2]……etc).Most of the published work performs a transformation step to express the input description into an intermediate representation (IR) such as Trimaran IR [6],control data flow graph(CDFG) [7] and VHDL-AST [2], and then apply the estimation process on the intermediate format.…”