FPGA side-channel receivers

Ji, Sun; Bittner, Ray; Eguro, Ken

doi:10.1145/1950413.1950462

Cited by 16 publications

(14 citation statements)

References 6 publications

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“…if ttSuccess = False then return Failed ttest.clock.disable() t ← t + k return Passed delay-line based sensors [19] and RO-based sensors [14,19]. We opted for the former, because it can capture voltage variations in time intervals as short as few ns.…”

Section: Power-supply Voltage Sensormentioning

confidence: 99%

Built-in Self-Evaluation of First-Order Power Side-Channel Leakage for FPGAs

Glamočanin

Coulon

Regazzoni

et al. 2020

Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

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Embedded and cyber-physical systems are pervading all aspects of our lives, including sensitive and critical ones. As a result, they are an alluring target for cyber attacks. These systems, whose implementation is often based on reconfigurable hardware, are typically deployed in places accessible to attackers. Therefore, they require protection against tampering and side-channel attacks. However, a side-channel resistant implementation of a security primitive is not sufficient, as it can be weakened by an adversary, aging, or environmental factors. To detect this, legitimate users should be able to evaluate the side-channel resistance of their systems not only when deploying them for the first time, but also during their entire service life. The most widespread and de facto standard methodology for measuring power side-channel leakage uses Welch's t-test. In practice, collecting the data for the t-test requires physical access to the device, a device-specific test setup, and the equipment for measuring the power consumption during device operation. Consequently, only a small number of cyber-physical systems deployed in the field can be tested this way and the tests to reevaluate the device resistance to side-channel attacks cannot be easily repeated. To address these issues, we present a design and an FPGA implementation of a built-in test for self-evaluation of the resistance to first-order power side-channel attacks. Once our test is triggered, the FPGA measures its own internal power-supply voltage and computes the t-test statistic in real time. Experimental results on two different implementations of the AES-128 algorithm demonstrate that the self-evaluation test is very reliable. We believe that this work is an important step towards the development of security sensors for the next generation of safe and robust cyber-physical systems. CCS CONCEPTS • Hardware → Reconfigurable logic and FPGAs; • Security and privacy → Tamper-proof and tamper-resistant designs; Sidechannel analysis and countermeasures.

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Section: Power-supply Voltage Sensormentioning

confidence: 99%

Built-in Self-Evaluation of First-Order Power Side-Channel Leakage for FPGAs

Glamočanin

Coulon

Regazzoni

et al. 2020

Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

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“…Although traditional covert-and side-channel attacks on FPGAs require physical access to the device [34], [49], temperature-and voltage-based remote FPGA attacks are possible. The works by Iakymchuk et al [18] and Tian and Szefer [36] lie in the former category, performing temperaturebased covert communications within an FPGA and between consecutive users of the same FPGA board respectively.…”

Section: B Remote Fpga Attacksmentioning

confidence: 99%

Reading Between the Dies: Cross-SLR Covert Channels on Multi-Tenant Cloud FPGAs

Giechaskiel

Rasmussen

Szefer

2019

2019 IEEE 37th International Conference on Computer Design (ICCD)

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Field-Programmable Gate Arrays (FPGAs) are becoming increasingly available via commercial cloud providers, which currently allocate devices on a per-user basis. As the underlying hardware is often underutilized, several proposals for multi-tenant use of FPGA resources have been brought forth, along with some initial work on security attacks in this setting. Simultaneously, high-end FPGAs are being produced with 2.5D integration of multiple distinct dies, called Super Logic Regions (SLRs), onto the same chip. Although one might expect that physical separation of logic onto separate dies could prevent multitenant attacks, this paper demonstrates for the first time that cross-SLR information leaks based on sensing voltage changes within the FPGA chip are possible, without physical access to or modification of the boards. The cross-SLR covert channel is characterized analytically and experimentally on five Xilinx Virtex UltraScale+ FPGAs, both locally and on the Amazon and Huawei clouds. Several configurations of the source transmitters and the sink receivers are tested, including their locations, types, and sizes. The power-based channel is shown to have a bandwidth upwards of 4.6 Mbps and accuracy of over 97.6%. Consequently, as physical separation of tenants onto separate dies (SLRs) is an insufficient countermeasure against information leaks, hardware-level architectural improvements are necessary to make secure multi-tenant FPGAs on shared clouds a reality.

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“…Oscillators with large n will have less variability across instances, which may help in applications that rely on uncalibrated sensor readings [Sun et al 2011]. However, with modern technologies, different oscillator instances can still be skewed by spatiallycorrelated variations, and thus calibration will in many cases still be required.…”

Section: Ring Oscillator Designmentioning

confidence: 99%

Low-cost sensing with ring oscillator arrays for healthier reconfigurable systems

Zick

Hayes

2012

ACM Trans. Reconfigurable Technol. Syst.

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Electronic systems on a chip increasingly suffer from component variation, voltage noise, thermal hotspots, and other subtle physical phenomena. Systems with reconfigurability have unique opportunities for adapting to such effects. Required, however, are low-cost, fine-grained methods for sensing physical parameters. This article presents powerful, novel approaches to online sensing, including methods for designing compact reconfigurable sensors, low-cost threshold detection, and several enhanced measurement procedures. Together, the approaches help enable systems to autonomously uncover a wealth of physical information. A highly efficient counter and improved ring oscillator are introduced, enabling an entire sensor node in just 8 Virtex-5 LUTs. We describe how variations can be measured in delay, temperature, switching-induced IR drop, and leakage-induced IR drop. We demonstrate the proposed approach with an experimental system based on a Virtex-5, instrumented with over 100 sensors at an overhead of only 1.3%. Results from thermally controlled experiments provide some surprising insights and illustrate the utility of the approach. Online sensing can help open the door to physically adaptive computing, including fine-grained power, reliability, and health management schemes for systems on a chip. ACM Reference Format:Zick, K. M. and Hayes, J. P. 2012. Low-cost sensing with ring oscillator arrays for healthier reconfigurable systems.

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FPGA side-channel receivers

Cited by 16 publications

References 6 publications

Built-in Self-Evaluation of First-Order Power Side-Channel Leakage for FPGAs

Built-in Self-Evaluation of First-Order Power Side-Channel Leakage for FPGAs

Reading Between the Dies: Cross-SLR Covert Channels on Multi-Tenant Cloud FPGAs

Low-cost sensing with ring oscillator arrays for healthier reconfigurable systems

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