FPGA-SPICE: A simulation-based power estimation framework for FPGAs

Abstract

Abstract-Mainstream Field Programmable Gate Array(FPGA) power estimation tools are based on probabilistic activity estimation and analytical power models. The power consumption of the programmable resources of FPGAs is highly sensitive to their configurations. Due to their highly flexible nature, the configurations of FPGAs routing multiplexers or Look Up Tables (LUTs) are really different from a design to another but current analytical power models cannot accurately capture the associated power differences. In this paper, we introduce a simulation-based power estimation framework for FPGAs, called FPGA-SPICE, which supports any FPGA architecture that can be described with an architectural description language. Our power estimation engine automatically generates accurate SPICE netlists according to the FPGA configurations and enables precise power analysis of FPGA architectures. SPICE testbenches can be generated at different level of complexity, denoted as fullchip-level, grid-level and component-level testbenches. Full-chiplevel testbenches dump the netlists associated with the complete FPGA fabric. To reduce simulation time, FPGA-SPICE can split the full-chip-level testbenches into grid-level testbenches, each of which consisting of a complete logic block netlist, or componentlevel testbenches, which consider individual circuit elements, i.e., multiplexers, LUTs, flip-flops, etc., separately. We show that the grid/component-level approach can achieve 14× speed-up with a moderate 14% accuracy loss, compared to the full-chip level. We also use FPGA-SPICE to study the power characteristics of a commercial FPGA architecture at different technology nodes. Experimental results show that the global routing architecture consumes 50% of the total power, the local routing architecture claims for 40% of the total power, and the remaining 10% comes from the LUTs and flip-flops.

Efficient power macromodeling approach for heterogeneously stacked 3d ICs using Bio-geography based optimization

“…By the early and accurate estimation of multiplier, blocks can help designers for the efficient designing of low-power applications [4]. An FPGA based model generates the SPICE netlist depending upon the architecture and also enables the precise power estimation of architecture [5].…”

FPGA-SPICE: A Simulation-Based Architecture Evaluation Framework for FPGAs

“…For instance, only fully-decoded multiplexer structures are supported in [15], while modern FPGAs typically employ twolevel or one-level multiplexer structures at advanced technology nodes. 3) Most previous works [1]- [12] focused on studying the core logic of FPGAs, while very limited works [14], [15] considered the full FPGA fabrics. Moreover, as different configuration peripheral circuits are used in commercial products [20]- [24], [29], limited work has been done to study their impacts on FPGAs.…”

“…Consequently, the architecture-level conclusions could be misleading. For instance, by under/overestimating the area/power contribution of FPGA components, the area/power breakdown results could be inaccurate, leading to wrong directions in optimizing FPGA architectures [10]- [12].…”

Circuit Design and Configuration for Low Power FPGAs

“…Research has been conducted for reducing simulation times for FPGAs. FPGA-SPICE ( [32]) extends VTR to allow for SPICE-level simulations on the individual FPGA sub-circuits, which could drastically reduce run-time for low-voltage simulations as well as increase the accuracy. Leveraging a flow similar to FPGA-SPICE could mitigate the low-voltage simulation problems, but FPGA-SPICE is currently limited to the same architectural and circuit-level flexibility as VTR.…”