FPGA-targeted high-level binding algorithm for power and area reduction with glitch-estimation

Abstract

Glitches (i.e. spurious signal transitions) are major sources of dynamic power consumption in modern FPGAs. In this paper, we present an FPGA-targeted, glitch-aware, highlevel binding algorithm for power and area reduction, accomplished via dynamic power estimation and multiplexer balancing. Our binding algorithm employs a glitch-aware dynamic power estimation technique derived from the FPGA technology mapper in [6]. High-level binding results are converted to VHDL, and synthesized with Altera's Quartus II software, targeting the Cyclone II FPGA architecture. Power characteristics are evaluated with the Altera PowerPlay Power Analyzer. The binding results of our algorithm are compared to LOPASS, a state-of-the-art low-power highlevel synthesis algorithm for FPGAs. Experimental results show that our algorithm, on average, reduces toggle rate by 22% and area by 9%, resulting in a decrease in dynamic power consumption of 19%. To the best of our knowledge this is the first high-level binding algorithm targeting FPGAs that considers glitch power.

An OpenCL-based parallel acceleration of aSobel edge detection algorithm Using IntelFPGA technology

“…The Kill A Watt EZ P4460 power meter device was used to measure the dynamic power consumption, as many studies, such as Bartram et al (2010), employ this device. For the FPGA platform, the Power Analyzer tool available within the Intel Quartus software can be used to profile full power consumption details; many studies adopted this tool when it was necessary to profile the energy or power dissipation (Cromar et al, 2009;Hossain et al, 2011;Shah et al, 2012). Although the static power consumption in a CPU-based platform is higher than in the FPGA-based platform, the focus in this study is to analyze the dynamic power consumption, which is considered here for comparison purposes.…”

High-level Synthesis for Low-power Design

“…Relevant Techniques Using low-power technologies Multiple threshold voltage [15], [49], [91], multiple supply voltage [12], [39], [47], [59], non-volatile memory [57] Scaling down the power for under-utilized resources Clock gating [1], [45], power gating [14], [16], [18], [31], behavioral observability don't care [22], [23], soft constraints [24], dynamic voltage and frequency scaling [46], [64], [82] Matching work to energy-efficient options Heterogeneous substrates [2], [3], [78], [87], [99], C-like parallel programming targeting FPGA [29], [72], [97] Cross-layer analysis Interconnect optimization [11], [13], [43], floorplanning optimization [38], [88], memory optimization [7], [21], [61], [95], high-level/logic synthesis [28] Trading-off other metrics for power Approximate hardware synthesis from behavioral description [67], error-constrained bit-width optimization [26], [63], [70] Spending power to save power Resource over-provisioning for hotspot reduction …”

“…[8] to efficiently calculate switching activities using high-level CDFG simulation and use switching activities to estimate power consumption. Based on a glitch-aware technology mapper [17], Cromar et al [28] further consider glitches, spurious switching activities, in their power estimation for additional power reduction during binding. We will present a detailed case study of this work in Section 3.2.…”

“…HLPower [28] is such a cross-layer approach, targeting glitch power reduction through glitch-aware binding that minimizes switching activity. The HLPower binding engine does register binding first and functional unit binding second.…”

Impact of FPGA architecture on resource sharing in high-level synthesis

“…Recent research on resource sharing that specifically targets FPGAs includes [9,8,5,14,4]. The work of Cong and Jiang [6] bears the most similarity to our own in that it applied graph-based techniques to identify commonly occurring patterns of operators in the HLS of FPGA circuits, and then shared such patterns in binding for resource reduction.…”