FPGA test and coverage

Toutounchi, S.; Lai, Andrea

doi:10.1109/test.2002.1041811

Cited by 43 publications

(11 citation statements)

References 3 publications

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“…These resources are vital to the functionality of FPGAs and thus testing them is pretty important. Generally, the exact users' way to configure the chip is not known during the test, so those interconnect resources must work properly under any user configuration, which is also known as application-independent testing [4,5,6,7,11]. Since the FPGA test time is dominated by the number of test configurations that are employed, the ultimate goal of interconnection testing is to detect maximum faults with minimum test configurations and to keep the adaptivity to different kinds of FPGAs at the same time [5,6,7,11].…”

Section: Introductionmentioning

confidence: 99%

A new automatic method for testing interconnect resources in FPGAs based on general routing matrix

Yang

Liang

Wang

et al. 2015

IEICE Electron. Express

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Testing of interconnect resources is one of the most important parts in FPGA testing, since most of the transistors in the chip are dedicated to interconnections. Conventional testing methods are no longer as efficient as before because of the various new types of interconnections and a lack of enough input output blocks (IOBs) in the FPGAs that are based on general routing matrix (GRM). This paper presents a new automatic method for testing FPGA interconnect resources in GRM-based FPGAs. This new method, testing line segments and programmable interconnect points (PIPs) in different stages, is applicable to all kinds of GRM-based FPGAs. Experimental results show that a total of 152 test configurations are sufficient to achieve 99.2% and 99.7% fault coverage for line segments and PIPs in Xilinx XC4VLX15 FPGA respectively and to largely reduce the number of IOBs required in the testing.

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Section: Introductionmentioning

confidence: 99%

A new automatic method for testing interconnect resources in FPGAs based on general routing matrix

Yang

Liang

Wang

et al. 2015

IEICE Electron. Express

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“…Almost 80% of transistors in an FPGA are inside this programmable routing network for programmable switches and buffers. In current FPGAs, more than eight layers of metal are used, most of them for routing resources [1].…”

Section: Introductionmentioning

confidence: 99%

Single fault reliability analysis in FPGA implemented circuits

Jahanirad

Mohammadi

Attarsharghi

2012

Thirteenth International Symposium on Quality Electronic Design (ISQED)

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Reliability analysis in FPGA implementation of logic circuits is an important issue in designing fault tolerant systems for faulty environments. In this paper an analytical method is developed for analyzing such systems. This method is based on signal probability propagation of faults from the location of appearance to final outputs of circuit.Single fault model is used for the faults occurred in routes and LUTs. In addition reconvergent fan-outs are handled using 16 correlation coefficients propagation approach. Experimental results show a good agreement between this method and Monte Carlo method for reliability analysis of MCNC benchmarks.

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“…Specifically, testing on reconfigurable devices generally requires the loading of a large number of configuration information sets containing a large number of test structures, and the loading of these sets, known as test configurations, consumes more than 90% of the test time required for reconfigurable devices [5] [6].…”

Section: Introductionmentioning

confidence: 99%

Test Compression for Dynamically Reconfigurable Processors

Inoue

Yamada

Yoneda

et al. 2010

2010 International Conference on Field Programmable Logic and Applications

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We present the world's first test compression technique that features automation of compression rules for test time reduction on dynamically reconfigurable processors. Evaluations on an actual 40-nm product show that our technique achieves a 2.7 times compression ratio for original configuration information (better than does GZIP), the peak decompression bandwidth of 1.6 GB/s, and 2.7 times shorter test times.

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FPGA test and coverage

Cited by 43 publications

References 3 publications

A new automatic method for testing interconnect resources in FPGAs based on general routing matrix

A new automatic method for testing interconnect resources in FPGAs based on general routing matrix

Single fault reliability analysis in FPGA implemented circuits

Test Compression for Dynamically Reconfigurable Processors

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