2010
DOI: 10.1007/978-3-642-16435-4_1
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FPGA Time-Bounded Unclonable Authentication

Abstract: Abstract. This paper introduces a novel technique for extracting the unique timing signatures of the FPGA configurable logic blocks in a digital form over the space of possible challenges. A new class of physical unclonable functions that enables inputs challenges such as timing, digital, and placement challenges can be built upon the delay signatures. We introduce a suite of new authentication protocols that take into account non-triviality of bitstream reverse-engineering in addition to the FPGA's unpreceden… Show more

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Cited by 18 publications
(17 citation statements)
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References 18 publications
(31 reference statements)
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“…There are only a polynomial number of challenges with respect to the number of SRAM cells. An FPGA-based PUF along with a suite of time-bounded authentication protocols is introduced in [11]. The PUF produces binary responses based on the difference between the clock speed and some combinational circuit delay.…”
Section: Related Workmentioning
confidence: 99%
“…There are only a polynomial number of challenges with respect to the number of SRAM cells. An FPGA-based PUF along with a suite of time-bounded authentication protocols is introduced in [11]. The PUF produces binary responses based on the difference between the clock speed and some combinational circuit delay.…”
Section: Related Workmentioning
confidence: 99%
“…with Ω k as specified in (13). Given the state |n, c , the H k are Gaussian-distributed with H k = 0.…”
Section: A Proof Of Lemmamentioning
confidence: 99%
“…It builds on a ideas and hardware architectures discussed already in [25]. Another closely related, but later idea is the concept of time-bounded authentication (TBA) [26], which has been suggested for identification schemes on FPGAs.…”
Section: F Related Workmentioning
confidence: 99%
“…The implementation of PPUFs presented in [24] could potentially be downscaled to become a SIMPL system, even though it would have to be carefully investigated how resilient such small-scale instances are against parallelization attacks. Another very interesting, FPGA-based candidate for SIMPLs is implicit in the work of [26].…”
Section: B Electrical Simpl Systemsmentioning
confidence: 99%