FPGA Trax Solver based on a neural network design

Fujimori, Takahiro; Akabe, Tomoya; Ito, Yoshizumi; Akagi, Kouta; Furukawa, Seiichi; Shinba, Hiroki; Tanibata, Aoi; Watanabe, Minoru

doi:10.1109/fpt.2015.7393119

Cited by 2 publications

(2 citation statements)

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“…The code uses approximately 70% of the Combinational ALUTs, 29% of the Total Block Memory Bits and 68% of the DSP blocks. The Trax solver design given in [17] again uses the Arria II GX processor of Altera and consumes 80% of the Combinational ALUTs, 63% of the Total Block Memory Bits and 25% of the dedicated logic registers. The Pong game code is implemented on a Nexys 2 Development board which has Spartan 3E FPGA in [18].…”

Section: Introductionmentioning

confidence: 99%

“…Thanks to the availability of one-to-one mapping and the spatial and temporal parallelism of the FPGAs, they are often used to implement real-time image processing applications [6][7][8][9][10]. One such application is the game code implementation on FPGAs such as Tetris [11], Connect6 [12][13], Blokus duo [14][15][16], Trax [17] and Pong [18][19]. In [11], Kuo et al design a tetris game code using the Spartan 3AN FPGA starter board of Xilinx.…”

Section: Introductionmentioning

confidence: 99%

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VHDL İle Tam Gömülü Bi̇r Tetri̇s Oyunu Gerçekleşti̇rmesi̇

Polat¹

2020

Ömer Halisdemir Üniversitesi Mühendislik Bilimleri Dergisi

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In this paper, a Tetris game code which runs on an FPGA development and education board is synthesized. To this end, an original Tetris game code that works solely on the FPGA board is designed in VHDL hardware description language. The novelty of this design lies in the fact that the Tetris code does not use any SRAM modules for storage unlike other embedded Tetris implementations published to date. What is more, the code uses a tile-mapped scheme in which the code groups certain pixels as a tile. Thus, a 1-bit register is enough for the current value of all the pixels that fall in the tile which improves the speed of the code and simplifies the design procedure. The code is written using VHDL hardware description language. Though Altera DE0 development and education board is used for the implementation, thanks to the usage of only the standard VHDL functions, the code can run on any other FPGA boards.

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Section: Introductionmentioning

confidence: 99%