FracNoC: A fractal on-chip interconnect architecture for System-on-Chip

Abstract

Sophisticated on-chip interconnects (OCIs) were recently proposed as a solution to non-scalable shared bus schemes for Systems-on-Chip (SoC) design and implementation. In this paper a new OCI architecture by adapting a fractal topology structure is introduced. Simulations were conducted to compare this topology with two common OCIs, 2D Mesh, and Torus, using a variety of traffic patterns. Results show that this fractal architecture achieves better performance while using little energy budget. Network on Chip; System on Chip; Fractal structures; simulations; performance evaluation; Nirgam I.978-1-4799-0838-7/13/$31.00 ©2013 IEEE