Fractional-N Frequency Synthesizer for Spread Spectrum Clock Generation Applications

Lai, Wen‐Cheng

doi:10.1109/apcap50217.2020.9246114

Cited by 2 publications

(1 citation statement)

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“…Some methods for reducing power consumption include gated leakage transistors (GALEOR), leakage control transistors (LECTOR), AVL, adiabatic logic, stack, and clock gating [18]. Power consumption while operating at higher frequencies requires power reduction techniques, one method involves dividing the VCO output used in the feedback path followed by circuitry that performs the division [20].…”

Section: Literature Reviewmentioning

confidence: 99%

Area and power efficient divide-by-32/33 dual-modulus pre-scaler using split-path TSPC with AVLS for frequency divider

Siddaiah,

Narsepalli,

Mittal

et al. 2023

Journal of Electrical Engineering

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Pre-scalers are electronic circuits used in phase-locked loops to multiply frequencies. This is achieved by dividing the high-frequency signals generated from a voltage-controlled oscillator. The high-frequency operation of pre-scaler circuits leads to significantly higher power consumption. To address this, D flip-flops (D-FF) realized using true-single phase clocking (TSPC) logic. The work suggests incorporating the Adaptive Voltage Level Source (AVLS) circuit with the Dual Modulus Pre-Scaler (DMPS) circuit to reduce power consumption. In addition to the incorporation of the AVLS circuit, pass transistor logic (PTL) used in the feedback, further minimizes transistors and power. This paper proposes three different designs for divide-by-32/33 DMPS circuit. The proposed-1 design combines regular TSPC-based D-FF with PTL in the feedback and an AVLS circuit, resulting in an average power reduction of 36.5%. The proposed-2 design employs split-path TSPC-based D-FF with logic gates and an AVLS circuit, achieving a power reduction of 46.9%. The proposed-3 design employs split-path TSPC-based D-FF with PTL in the feedback and an AVLS circuit, achieving a significant power reduction of 47.8% compared to the existing DMPS circuit and transistor count by 9.1%. The proposed circuits are realized using a CMOS 180 nm technology node. Cadence Virtuoso and Spectre tools are used. The proposed divide-by-32/33 DMPS circuits also realized in the CMOS 45 nm technology node to verify the functionality in the lower technology node. A power reduction of 46.86% observed when compared to the reference circuit. The proposed designs are both power- and area-efficient, making them promising solutions for minimizing power consumption in pre-scaler circuits.

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Section: Literature Reviewmentioning

confidence: 99%