Frame-by-frame speech recognition as hardware decoding on FPGA devices

Abstract

This paper proposes frame-by-frame speech recognition as a hardware decoder on Field Programmable Gate Arrays (FPGAs). As a first step for FPGA implementation, Voice Activity Detection (VAD) using second order autocorrelation and a speech recognition decoder using formant frequency distances were evaluated. The hardware decoding was then implemented on an FPGA emulator. The VAD and decoder were demonstrated to be effective, and hence could be suitable for implementation on FPGA devices.