1969
DOI: 10.1109/jssc.1969.1049950
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Frequency and power limitations of Class-D transistor amplifiers

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Cited by 74 publications
(10 citation statements)
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“…The computed amplitudes of output current I O and the power P O are a little bit larger then those obtained by (8,9). Conduction losses may be estimated using the value of I O obtained by simulation and formula (11). On the contrary, switching losses caused by charging and discharging output capacitances of both power transistors are obtained exactly…”
Section: Second Stage -Simulation On Idealized Switch Levelmentioning
confidence: 85%
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“…The computed amplitudes of output current I O and the power P O are a little bit larger then those obtained by (8,9). Conduction losses may be estimated using the value of I O obtained by simulation and formula (11). On the contrary, switching losses caused by charging and discharging output capacitances of both power transistors are obtained exactly…”
Section: Second Stage -Simulation On Idealized Switch Levelmentioning
confidence: 85%
“…3); transistors T 1 , T 2 operating in non-ZVS and ZCS mode are driven alternatively by a periodic input signal [11], [25]. The output circuit is a selective series-resonant circuit with the resonant frequency equal to the input-signal frequency.…”
Section: A Properties Of the Considered Amplifiermentioning
confidence: 99%
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“…At high frequencies, the power loss during switching transitions contributes substantially to the total power loss [25]. In order to increase the efficiency of the class-D PA, a technique based on the use of a dead-time between the switching of the low-side and high-side switches can be used [21].…”
Section: Programmable Delay Line For Dead-time Adjustmentmentioning
confidence: 99%
“…T HE efficiency of Class D voltage-switching inverters [1], [2] is low at high frequencies due to switching losses [3], [4]. To reduce switching losses, zero-voltage switching (ZVS), or soft-switching, techniques have been applied [5]- [9].…”
Section: Introductionmentioning
confidence: 99%