Frequency-Based Sensor Interface with Dynamic Offset Compensation

Abstract

Sensor interfaces need to be robust and accurate for many applications. This is more challenging for sensor systems operating in radiation environments because the mismatch between components grows as a result of the absorbed total ionizing dose (TID). In frequency-based sensor interfaces, the frequency drift of the voltage-controlled oscillator (VCO) can create dynamic output offset, gain, and linearity errors unless a calibration algorithm is included. In this paper, a digital intensive dynamic offset cancelation technique is proposed for an open loop VCO-based sensor to digital converter, which is achieved by making periodic adjustments to the average center biasing voltage of one of the VCOs in a differential architecture, in effect to make their center frequencies match. A simulation of the behavioral model of the proposed architecture was developed and hardware implementation of the whole system was performed on an FPGA by emulating, with digital modules, the characteristics of the two VCO outputs modulated with differential inputs. The results showed that the output offset error was reduced from around 5% to 0.1% for a relative oscillators’ drift close to 10% of the tuning range, and the SNDR is relatively maintained when subjected to variable relative VCO drifts.

Drift Resilient Frequency-Based Sensor Interface Architectures with Adaptive Clock Frequency

“…The block of the detailed implemented structure in this work is illustrated in Figure 6. To perform dynamic performance tests, the digital differential input generator synthesizes differential digital sine inputs using a sixteen-stage coordinate rotation digital computer (CORDIC) algorithm as in [16]. On the other hand, to estimate the static performance, differential dc inputs with peak values are used.…”

“…VFCs with a frequency of up to 100 MHz have been reported with a non-linearity below 0.06% [22]. Based on this, to assess the performance of the first architecture, the proposed structure is implemented on a field-programmable gate array (FPGA) where sine-modulated VFC outputs are emulated with digital components as in [16] with around 0.1% non-linearity. The block of the detailed implemented structure in this work is illustrated in Figure 6.…”

“…To address a mismatch issue between the two VCOs in open loop frequency-based sensor-to-digital converters, a dynamic offset cancelation scheme based on a periodic adjustment of the center biasing voltage of one of the VCOs was demonstrated in [16], which successfully mitigated the offset error due to the relative drift of the VCOs. However, this mechanism lacks a way to correct gain error problems that arise.…”