Frequency Dependent Charge-Pumping, How deep does it probe?

Wang, Y.; Lee, V.; Cheung, Kin P.

doi:10.1109/iedm.2006.346898

Cited by 18 publications

(2 citation statements)

References 8 publications

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“…This sets a clear tunneling time restriction which allows us to unambiguously examine the validity of the elastic tunneling picture. One can estimate the expected tunneling time from the tunneling front model [28][29][30][31]. This model yields the time required for a "tunneling front" to reach a given dielectric depth with an assumption of the time zero tunneling depth (τ 0 ).…”

Section: Discussionmentioning

confidence: 99%

Random telegraph noise in highly scaled nMOSFETs

Campbell

Qin

Cheung

et al. 2009

2009 IEEE International Reliability Physics Symposium

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Recently, 1/f and random telegraph noise (RTN) studies have been used to infer information about bulk dielectric defects' spatial and energetic distributions. These analyses rely on a noise framework which involves charge exchange between the inversion layer and the bulk dielectric defects via elastic tunneling. In this study, we extracted the characteristic capture and emission time constants from RTN in highly scaled nMOSFETs and showed that they are inconsistent with the elastic tunneling picture dictated by the physical thickness of the gate dielectric (1.4 nm). Consequently, our results suggest that an alternative model is required and that a large body of the recent RTN and 1/f noise defect profiling literature very likely needs to be re-interpreted.

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Section: Discussionmentioning

confidence: 99%

Random telegraph noise in highly scaled nMOSFETs

Campbell

Qin

Cheung

et al. 2009

2009 IEEE International Reliability Physics Symposium

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“…For a given difference between two discharge times, a larger incremental change of V FB implies a higher density of "bulk" traps at a particular location in the gate stack. The detrapping time for "bulk" traps situated at 1 nm from the Si/IL interface (corresponding to the IL/HfZrO interface denoted by the vertical dotted line) is estimated to be 40 ms [165].…”

Section: Traps Profile By Pulse C-v Measurementmentioning

confidence: 99%

Nanoscale characterization of advanced high-?? gate dielectric stacks via scanning tunneling microscopy

Yew¹

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My sincere gratitude to my supervisor, Prof. Ang Diing Shenp from Nanyang Technological University (NTU), for his sound technical guidance, inspiring ideas, constructive discussions and constant encouragement throughout the course of my Ph.D research works. His immense knowledge in device physics, sharp analytical skills, effective writing skills, high research integrity and great passion in research have sparked my growing enthusiasm in research field. He is a kind and committed person, who is willing to spend time and patiently works things out with us whenever we faced difficulties in our works. Prof. D. S. Ang is more than a research supervisor to me; he has always provided me with invaluable advices, be it in research, career or life. I am very grateful and lucky to have the opportunity to work under Prof. D. S. Ang's supervision. I would like to express my sincere gratitude to Prof. Pey Kin Leong (during his tenure with NTU) for granting me access to the ultra-high vacuum scanning tunneling microscopy (UHV-STM) system and Dr. Ong Yi Ching (currently with TSMC Taiwan) for patiently training me in handling the UHV-STM system. She has been very kind to share her technical experience in the high-κ metal oxide characterization using STM. My appreciation to Dr. Lakshmi Kanta Bera for his technical advices on device fabrication process. This project is supported in part by the Singapore Ministry of Education under a research grant MOE2009-T2-1-050 and in part by the NTU.

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Characterizing Defects Responsible for Charge Transport Characteristics at Interfaces of Nano-Thick Materials Stacks

Bersuker

Watkins

Shluger

2016

Oxide Materials at the Two-Dimensional Limit

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Major functioning blocks in modern devices employed in a variety of applications (electronics, energy harvesting, sensors, etc.) comprise of stacks of nm-thin layers of dielectric materials in contact with conductive electrodes (semiconductors, metals). The performance and reliability of these devices are affected by charge transfer characteristics of these multilayer stacks. We discuss collaboration between electrical measurements and computational modeling leading to identification of defects responsible for degradation phenomena in nm-thin dielectric films employed as gate dielectrics in metal oxide field effect transistors

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Frequency Dependent Charge-Pumping, How deep does it probe?

Cited by 18 publications

References 8 publications

Random telegraph noise in highly scaled nMOSFETs

Random telegraph noise in highly scaled nMOSFETs

Nanoscale characterization of advanced high-?? gate dielectric stacks via scanning tunneling microscopy

Characterizing Defects Responsible for Charge Transport Characteristics at Interfaces of Nano-Thick Materials Stacks

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