Frequency Optimization Objective during System Prototyping on Multi-FPGA Platform

Abstract

Multi-FPGA hardware prototyping is becoming increasingly important in the system on chip design cycle. However, after partitioning the design on the multi-FPGA platform, the number of inter-FPGA signals is greater than the number of physical connections available on the prototyping board. Therefore, these signals should be time-multiplexed which lowers the system frequency. The way in which the design is partitioned affects the number of inter-FPGA signals. In this work, we propose a set of constraints to be taken into account during the partitioning task. Then, the resulting inter-FPGA signals are routed with an iterative routing algorithm in order to obtain the best multiplexing ratio. Indeed, signals are grouped and then routed using the intra-FPGA routing algorithm: Pathfinder. This algorithm is adapted to deal with the inter-FPGA routing problem. Many scenarios are proposed to obtain the most optimized results in terms of prototyping system frequency. Using this technique, the system frequency is improved by an average of 12.8% compared to constructive routing algorithm.

Scalable Hardware Mechanism for Partitioned Circuits Operation

“…A set of constraints during the partitioning task and an iterative routing algorithm to obtain the best multiplexing ratio for inter-FPGA signals have been researched [5]. This research focuses on a method to partition a circuit efficiently but our approach focuses on the way to operate the partitioned circuits in high speed.…”