From C/C++ Code to High-Performance Dataflow Circuits

Abstract

High-level synthesis (HLS) tools typically generate statically scheduled datapaths. Static scheduling implies that the resulting circuits have a hard time exploiting parallelism in code with potential memory dependences, with control dependences, or where performance is limited by long latency control decisions. In this work, we describe an HLS approach which generates dynamically scheduled, dataflow circuits out of imperative code. We detail a complete set of rules to transform a standard compiler intermediate representation into a high-performance dataflow circuit that is able to dynamically resolve memory dependences and adapt its behavior on the fly to particular control flow decisions and operation latencies. Compared to a traditional HLS tool, the result is a different trade-off between performance and circuit complexity: statically scheduled circuits display the best performance per cost in regular applications, but general-purpose, irregular, and control-dominated computing tasks require the runtime flexibility of dynamic scheduling. Therefore, enabling dynamic behavior in HLS is key to dealing with the increasing computational demands of new contexts and broader application domains.

A High-Frequency Load-Store Queue with Speculative Allocations for High-Level Synthesis

“…Dynamically Scheduled High-Level Synthesis Dynamically scheduled circuits rely on the theory of latency-insensitive design formalized by Carloni et al [11] and simplified by Cortadella et al for synchronous circuits [12]. In latency-insensitive designs, the communication between modules is decoupled from their cycle behavior, allowing for dataflow scheduling of compute circuits [8], [13]- [16]. The most recent fully dynamically scheduled HLS tool is Dynamatic proposed by Josipović et al [8].…”

“…In latency-insensitive designs, the communication between modules is decoupled from their cycle behavior, allowing for dataflow scheduling of compute circuits [8], [13]- [16]. The most recent fully dynamically scheduled HLS tool is Dynamatic proposed by Josipović et al [8]. Dynamatic is based on the LLVM compiler framework [17] translating its Control and Data Flow Graph (CDFG) SSA representation into a dataflow circuit.…”

“…The higher area usage is often acceptable, but a higher critical path means that the final design synthesized on FPGA hardware is not able to achieve the frequencies achievable by static HLS. The critical path increase is due to using LSQs, and due to using buffers with a zero cycle write-to-read latency (called transparent buffers in Dynamatic [8]) where static HLS can use a simple wire. Several works have tackled the critical path overhead of Dynamatic.…”

“…Dynamic HLS uses dataflow scheduling to trigger the execution of operations at runtime based on the availability of data, rather than a static compile-time schedule. Dynamatic [8], the most recent example of a dynamic HLS tool, has shown that this approach can successfully accelerate codes where compile-time information needed by modulo scheduling is lacking. For our example code from fig.…”

“…1c. However, dynamic HLS incurs non-trivial resource and critical path overheads [8]. On codes that require dynamically scheduled memory operations, the highest overhead comes from loadstore queue (LSQ) structures.…”