From energy‐delay metrics to constraints on the design of digital circuits

Abstract

SUMMARYIn this paper, the adoption of general metrics of the energy-delay tradeoff is investigated to achieve energyefficient design of digital CMOS very large-scale integrated circuits. Indeed, as shown in a preliminary analysis on the performance of various commercial microprocessors, a wide range of E i D j metrics is typically adopted. Physical interpretation and interesting properties for the designs minimizing E i D j metrics are provided together with the adoption of the Logical Effort theory to define practical design constraints. Two design examples in a 65-nm CMOS technology are also reported to exemplify the theoretical results.

PVT variations in differential flip-flops: A comparative analysis

“…To explore the considered topologies across a wide range of design targets, transistors were sized to minimize the energydelay (E-D) figure of merit E i D j , with i=1, 2 and 3 and j=1, as well as i=1, j=1, 2 and 3 [10], [11]. The transistor sizes were optimized according to the strategy in [12], with layout parasitics estimated and included in the transistor-level optimization.…”

“…The simulation strategy in [10] was adopted to evaluate the timing parameters, the energy and the leakage for each FF topology. In particular, the following FF parameters were evaluated under the above variations: • minimum data-to-output (D-Q) delay, as representative of the impact on the system performance; • energy per cycle E, defined as average energy across all possible data transitions with assigned activity [6]- [7];…”

Analysis and comparison of variations in double edge triggered flip-flops

“…The simulation strategy in [12] was adopted to evaluate the timing parameters, the energy and the leakage for each FF topology. In particular, the following FF parameters were evaluated under the above variations:…”

“…These loads are representative of light, moderate and heavy load, respectively. To explore the considered topologies across a wide range of design targets, transistors were sized to minimize the energy-delay (E-D) figure of merit E i D j , with i=1, 2 and 3 and j=1, as well as i=1, j=1, 2 and 3 [12], [17]. The transistor sizes were optimized according to the strategy in [18], with layout parasitics estimated and included in the transistor-level optimization.…”

Flip-Flop Design in Nanometer CMOS

“…In the following, a model accounting for the above contributions is summarized [7,8]. This model aims at the extraction of a factor v featuring a logic gate and such that the overall gate energy E is simply expressed as linearly related to the input capacitance C IN , i.e.…”