From online fault detection to fault management in Network-on-Chips: A ground-up approach

Azad, Siavoosh Payandeh; Niazmand, Behrad; Janson, Karl; George, Nevin; Oyeniran, Adeboye Stephen; Putkaradze, Tsotne; Kaur, Apneet; Raik, Jaan; Jervan, Gert; Ubar, Raimund; Hollstein, Thomas

doi:10.1109/ddecs.2017.7934565

Cited by 17 publications

(6 citation statements)

References 25 publications

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“…In order to evaluate the performance of the proposed Distributed DoS Detection systems presented in Section 6 (i.e., CPRD and CPDD), they have been implemented on the RTL level and integrated to the Bonfire framework [19]. Traffic generators included in the Bonfire platform were leveraged for simulating normal traffic and DoS attacks on 4 × 4 mesh NoC-based MPSoC scenarios.…”

Section: Resultsmentioning

confidence: 99%

“…The evaluation of the related works shows that the DoS attack avoidance approaches require significant additional hardware effort in the routers and the system. Since scalable NoCs need an overall dependability management [19], the router size should be as minimal as possible (e.g., no virtual channels).…”

Section: Dos Attack Detection and Recoverymentioning

confidence: 99%

“…Each network tile consists of a wormhole switching router equipped with fault tolerance mechanisms and a Network Interface (NI), which is connected to the local resource. The routers use credit-based flow-control and support any turn-model-based minimal path adaptive routing algorithm [19,20]. Figure 1a shows a block diagram of the credit-based router used in this work.…”

Section: Router Architecturementioning

confidence: 99%

“…Hence, this architecture is called Collision Point Router Detection (CPRD) (The code is available for download at [29]). We propose two main modifications to the Bonfire NoC project [19]: (i) addition of the local and end-to-end delay and router information to the packet's tail, and (ii) introduction of the monitors in the routers.…”

Section: Collision Point Router Detection (Cprd) Architecturementioning

confidence: 99%

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DoS Attack Detection and Path Collision Localization in NoC-Based MPSoC Architectures

Chaves

Azad

Hollstein

et al. 2019

JLPEA

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Denial of Service (DoS) attacks are an increasing threat for Multiprocessor System-on-Chip (MPSoC) architectures. By exploiting the shared resources on the chip, an attacker is able to prevent completion or degrade the performance of a task. This is extremely dangerous for MPSoCs used in critical applications. The Network-on-Chip (NoC), as a central MPSoC infrastructure, is exposed to this attack. In order to maintain communication availability, NoCs should be enhanced with an effective and precise attack detection mechanism that allows the triggering of effective attack mitigation mechanisms. Previous research works demonstrate DoS attacks on NoCs and propose detection methods being implemented in NoC routers. These countermeasures typically led to a significantly increased router complexity and to a high degradation of the MPSoC’s performance. To this end, we present two contributions. First, we provide an analysis of information that helps to narrow down the location of the attacker in the MPSoC, achieving up to a 69% search space reduction for locating the attacker. Second, we propose a low cost mechanism for detecting the location and direction of the interference, by enhancing the communication packet structure and placing communication degradation monitors in the NoC routers. Our experiments show that our NoC router architecture detects single-source DoS attacks and determines, with high precision, the location and direction of the collision, while incurring a low area and power overhead.

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Section: Resultsmentioning

confidence: 99%

Section: Dos Attack Detection and Recoverymentioning

confidence: 99%

Section: Router Architecturementioning

confidence: 99%

Section: Collision Point Router Detection (Cprd) Architecturementioning

confidence: 99%

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DoS Attack Detection and Path Collision Localization in NoC-Based MPSoC Architectures

Chaves

Azad

Hollstein

et al. 2019

JLPEA

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“…Single-dimension verification campaigns ignoring interdependencies between the dimensions may lead to gaps in the overall electronic system quality. As an example, let us consider an actual verification campaign of an open-source NoC framework Bonfire [57], [58].…”

Section: A Motivational Examplementioning

confidence: 99%

Towards Multidimensional Verification: Where Functional Meets Non-Functional

Jenihhin

Lai

Ghasempouri

et al. 2018

2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)

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Trends in advanced electronic systems' design have a notable impact on design verification technologies. The recent paradigms of Internet-of-Things (IoT) and Cyber-Physical Systems (CPS) assume devices immersed in physical environments, significantly constrained in resources and expected to provide levels of security, privacy, reliability, performance and low power features. In recent years, numerous extra-functional aspects of electronic systems were brought to the front and imply verification of hardware design models in multidimensional space along with the functional concerns of the target system. However, different from the software domain such a holistic approach remains underdeveloped. The contributions of this paper are a taxonomy for multidimensional hardware verification aspects, a state-of-the-art survey of related research works and trends towards the multidimensional verification concept. The concept is motivated by an example for the functional and power verification dimensions.

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RTOS Solution for NoC-Based COTS MPSoC Usage in Mixed-Criticality Systems

Avramenko

Violante

2019

J Electron Test

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From online fault detection to fault management in Network-on-Chips: A ground-up approach

Cited by 17 publications

References 25 publications

DoS Attack Detection and Path Collision Localization in NoC-Based MPSoC Architectures

DoS Attack Detection and Path Collision Localization in NoC-Based MPSoC Architectures

Towards Multidimensional Verification: Where Functional Meets Non-Functional

RTOS Solution for NoC-Based COTS MPSoC Usage in Mixed-Criticality Systems

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