From RTL to silicon: The case for automated debug

Veneris,; Keng,; Safarpour,

doi:10.1109/aspdac.2011.5722204

Cited by 5 publications

(2 citation statements)

References 21 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…We refer to each such set of N blocks as a solution of cardinality N . These solutions help manage the tremendous debugging complexity of modern designs [18] by significantly limiting the potentially buggy lines in the RTL. SAT-based automated design debugging [4,11] encodes the debugging problem as a propositional formula whose satisfying assignments correspond to debugging solutions.…”

Section: Design Debuggingmentioning

confidence: 99%

Debugging with dominance: On-the-fly RTL debug solution implications

Mangassarian

Veneris

Smith

et al. 2011

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

Self Cite

View full text Add to dashboard Cite

Design debugging has become a resource-intensive bottleneck in modern VLSI CAD flows, consuming as much as 60% of the total verification effort. With typical design sizes exceeding the half-million synthesized gates mark, the growing number of blocks to be examined dramatically slows down the debugging process. The aim of this work is to prune the number of debugging iterations for finding all potential bugs, without affecting the debugging resolution. This is achieved by using structural dominance relationships between circuit components. More specifically, an iterative fixpoint algorithm is presented for finding dominance relationships between multiple-output blocks of the design. These relationships are then leveraged for the early discovery of potential bugs, along with their corrections, resulting in significant debugging speed-ups. Extensive experiments on real industrial designs show that 66% of solutions are discovered early due to dominator implications. This results in consistent performance gains in all cases and a 1.7x overall speed-up for finding all potential bugs, demonstrating the robustness and practicality of the proposed approach.

show abstract

Section: Design Debuggingmentioning

confidence: 99%

Debugging with dominance: On-the-fly RTL debug solution implications

Mangassarian

Veneris

Smith

et al. 2011

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

Self Cite

View full text Add to dashboard Cite

show abstract

“…Due to advancements in formal engines, most modern debugging techniques use Boolean Satisfiability (SAT) solvers [5]. The problem is encoded as a SAT instance, where each satisfying assignment corresponds to a potential bug location, called a solution [8]. Each solution consists of a (set of) circuit block(s) or RTL line(s), that can be modified to fix the erroneous behavior in the counter-example trace.…”

Section: Introductionmentioning

confidence: 99%

Non-solution implications using reverse domination in a modern SAT-based debugging environment

Le¹,

Mangassarian²,

Keng³

et al. 2012

2012 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

View full text Add to dashboard Cite

Abstract-With the growing complexity of VLSI designs, functional debugging has become a bottleneck in modern CAD flows. To alleviate this cost, various SAT-based techniques have been developed to automate bug localization in the RTL. In this context, dominance relationships between circuit blocks have been recently shown to reduce the number of SAT solver calls, using the concept of solution implications. This paper first introduces the dual concepts of reverse domination and non-solution implications. A SAT solver is tailored to leverage reverse dominators for the early on-the-fly detection of bug-free components. These are nonsolution areas and their early pruning significantly reduces the the debugging search-space. This process is expedited by branching on error-select variables first. Extensive experiments on tough real-life industrial debugging cases show an average speedup of 1.7x in SAT solving time over the state-of-the-art, a testimony of the practicality and effectiveness of the proposed approach.

show abstract