From wafer-level gate-oxide reliability towards ESD failures in advanced CMOS technologies

Kerber, A.; Röhner, M.; Wallace, C. A.; O'Riain, Lincoln; Kerber, M.

doi:10.1109/ted.2006.870517

Cited by 14 publications

(2 citation statements)

References 7 publications

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“…It can be observed that after pre-stress the shape parameter of the t BD distributions is reduced and t 63% , the time for which 63% of the samples have failed is shifted to a lower value. Similar results have been obtained in [7] on a 1.5 nm thick layer with a 1.2 µm 2 stress area and a much smaller pulse amplitude and in [8] on a 2.8 nm gate oxide with a 10 µm 2 area. Using eq.…”

Section: B Effect Of Voltage Pulses On the Sion Layersupporting

confidence: 88%

Nanoscale Characterization of High-K/IL Gate Stack TDDB Distributions After High-Field Prestress Pulses

Foissac

Blonkowski

Kogelschatz

2015

IEEE Trans. Device Mater. Relib.

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The effect of single nondestructive pulsed voltage prestresses on the time to breakdown distributions of a SiON/ HfSiON bilayer gate stack is investigated at nanometric scale using an atomic force microscope in conduction mode under ultrahigh vacuum. The results are compared with the degradation due to a voltage pulse of the SiON layer alone. It is found that only the shape parameters of the distributions are affected by the prestress pulses. This effect is then discussed in terms of a progressive degradation starting at the Si/SiON interface, and an extrapolation formula is given to predict the decrease of the time to breakdown of the bilayer gate stack as a function of the prestress pulse parameters.

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Section: B Effect Of Voltage Pulses On the Sion Layersupporting

confidence: 88%

Nanoscale Characterization of High-K/IL Gate Stack TDDB Distributions After High-Field Prestress Pulses

Foissac

Blonkowski

Kogelschatz

2015

IEEE Trans. Device Mater. Relib.

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“…The electric field in equation (1) and (2) could thus be simplified to stressed voltage. Another empirical model, known as power-law model [12,13,14], that concerns the voltage dependence of oxide breakdown and the junction breakdown is shown in equation (3):…”

Section: Introductionmentioning

confidence: 99%

Temperature-dependent power-law model for submicron CMOS circuits EOS breakdown study

Tseng

Chang

2016

IEICE Electron. Express

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A temperature-dependent power-law model to simulate the pulsing EOS breakdown in CMOS integrated circuits (ICs) was proposed and evaluated in this study. It is a logarithm form of power-law model inversely related to the temperature. Fitting the results from the stressing of different commercial ICs with the grounded-gate NMOS (GGNMOS) ESD circuits by the electrical pulses indicated that the new model displayed comparable accuracy to the traditional E model/thermochemical model at constant/room temperature. When temperature changed, however, the new model had a better relationship in regression. The temperature-dependent power-law model could be used to evaluate the EOS window design of integrated circuits and be implemented into the components classification for the assembly line's quality control.

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Dielectric Breakdown of Gate Oxides: Physics and Experiments

Strong¹,

Wu²,

Vollertsen³

et al. 2009

Reliability Wearout Mechanisms in Advanced CMOS Technologies

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From wafer-level gate-oxide reliability towards ESD failures in advanced CMOS technologies

Cited by 14 publications

References 7 publications

Nanoscale Characterization of High-K/IL Gate Stack TDDB Distributions After High-Field Prestress Pulses

Nanoscale Characterization of High-K/IL Gate Stack TDDB Distributions After High-Field Prestress Pulses

Temperature-dependent power-law model for submicron CMOS circuits EOS breakdown study

Dielectric Breakdown of Gate Oxides: Physics and Experiments

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