Front-end electronics and trigger systems—Status and challenges

Spieler, H.

doi:10.1016/j.nima.2007.07.025

Cited by 9 publications

(3 citation statements)

References 57 publications

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“…However the high particle density foreseen in the innermost layers of future experiments, is unaffordable for present front-end architectures [3]. In a flavor factory like SuperB [4] the expected particle flux foreseen at 1 cm of radius is 1 25M particle/(s · cm 2 ), and, foreseeing a clustering factor of 4, the hit rate raises to 100 MHz for 1 cm 2 of sensor area.…”

Section: Pos(rd09)042mentioning

confidence: 99%

Efficiency and readout architectures for large matrix of pixels

Gabrielli¹,

Giorgi²

2010

Proceedings of 9th International Conference on Large Scale Applications and Radiation Hardness of Semiconductor Detectors — PoS

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We present a digital readout architecture for a silicon pixel matrix sensor. It has been developed to cope with high hit rates, above 1 MHz/mm 2 for matrices greater than 80K pixels. This technology can be implemented inside a silicon MAPS device (Monolithic Active Pixel Sensor): a highresolution particle detector which integrates on the same bulk the sensor matrix and the CMOS logic for readout. The architecture proposed is based on three main concepts. In first place the readout of the hits is performed by activating one column at a time; all the fired pixels on the active column are read, sparsified and reset in parallel in one clock cycle. This implies the use of global signals across the sensor matrix, the consequent reduction of metal interconnections improves the active area while maintaining a high granularity (down to 40 µm of pixel pitch). Secondly, the activation for readout takes place only for those columns overlapping with a certain fired area, thus reducing the sweeping time of the whole matrix and reducing the pixel dead-time. Third, the sparsification (x-y address labeling of the hits) is performed with a lower granularity respect to single pixels, by addressing vertical zones of 8 pixels each. The fine-grain Y resolution is achieved by appending the zone pattern to the zone address of a hit. We show the benefits of this technique in presence of clusters. The main features of the readout architecture are described, then we presents the results obtained with a simulation of the VHDL readout model.

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Section: Pos(rd09)042mentioning

confidence: 99%

Efficiency and readout architectures for large matrix of pixels

Gabrielli¹,

Giorgi²

2010

Proceedings of 9th International Conference on Large Scale Applications and Radiation Hardness of Semiconductor Detectors — PoS

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“…The higher-level architecture of the PEM system underdevelopment is shown. Four front-end electronic blocks are responsible for analogue signal detection, each one directly connected to the top (bottom) of one plane of crystals [5]. Amplifiers and analogue multiplexer integrated circuits (ASIC1) are the main constituting components of the front-end blocks.…”

Section: Introductionmentioning

confidence: 99%

Performance improvement for a real time medical diagnosis system

M¹,

Suresh²,

MurugaPrasasd³

2012

2012 International Conference on Computing, Electronics and Electrical Technologies (ICCEET)

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Electronic equipments are finding vast application in medical field. Constant efforts are made for improving the performance of the system. Clear PEM scanner is an advanced instrument used in the field of breast cancer detection. The system is very complicated as the output from PEM is coming out through 12,228 channels. The time taken for transfer of data is high. In this paper a new design strategy for performing read out of the data from the sensor is presented.The design improves the overall performance of the system. The total pixels are divided into different sub matrices and a single column is read at a time. The system also provides high parallel processing technique there by wastage of time is avoided.978-1-4673-0210-4112/$31.00 ©2012 IEEE

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“…For example hybrid pixel sensors have been used for the ATLAS [1] and CMS [2] trackers at LHC. However the high particle density foreseen in the innermost layers of future experiments is unaffordable for present front-end architectures [3]. In a flavor factory like SuperB [4] the expected particle flux foreseen at 1 cm of radius is 1 25M particle s −1 cm −2 , and, foreseeing a clustering factor of 4, the hit rate raises to 100 MHz for 1 cm 2 of sensor area.…”

Section: Introductionmentioning

confidence: 99%

A high efficiency readout architecture for a large matrix of pixels.

Gabrielli¹,

Giorgi²

2010

J. Inst.

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A high efficiency readout architecture for a large matrix of pixels. ABSTRACT: In this work we present a fast readout architecture for silicon pixel matrix sensors that has been designed to sustain very high rates, above 1 MHz/mm 2 for matrices greater than 80k pixels. This logic can be implemented within MAPS (Monolithic Active Pixel Sensors), a kind of high resolution sensor that integrates on the same bulk the sensor matrix and the CMOS logic for readout, but it can be exploited also with other technologies. The proposed architecture is based on three main concepts. First of all, the readout of the hits is performed by activating one column at a time; all the fired pixels on the active column are read, sparsified and reset in parallel in one clock cycle. This implies the use of global signals across the sensor matrix. The consequent reduction of metal interconnections improves the active area while maintaining a high granularity (down to a pixel pitch of 40 µm). Secondly, the activation for readout takes place only for those columns overlapping with a certain fired area, thus reducing the sweeping time of the whole matrix and reducing the pixel dead-time. Third, the sparsification (x-y address labeling of the hits) is performed with a lower granularity with respect to single pixels, by addressing vertical zones of 8 pixels each. The fine-grain Y resolution is achieved by appending the zone pattern to the zone address of a hit. We show then the benefits of this technique in presence of clusters. We describe this architecture from a schematic point of view, then presenting the efficiency results obtained by VHDL simulations.

show abstract

Front-end electronics and trigger systems—Status and challenges

Cited by 9 publications

References 57 publications

Efficiency and readout architectures for large matrix of pixels

Efficiency and readout architectures for large matrix of pixels

Performance improvement for a real time medical diagnosis system

A high efficiency readout architecture for a large matrix of pixels.

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