Frontiers of silicon-on-insulator

Abstract

Silicon-on-insulator (SOI) wafers are precisely engineered multilayer semiconductor/dielectric structures that provide new functionality for advanced Si devices. After more than three decades of materials research and device studies, SOI wafers have entered into the mainstream of semiconductor electronics. SOI technology offers significant advantages in design, fabrication, and performance of many semiconductor circuits. It also improves prospects for extending Si devices into the nanometer region (<10 nm channel length). In this article, we discuss methods of forming SOI wafers, their physical properties, and the latest improvements in controlling the structure parameters. We also describe devices that take advantage of SOI, and consider their electrical characteristics.

Silicon on Insulator Technology Review

“…SOI devices also appear to offer a sustainable, long-term pathway beyond the multiple barriers to scaling planar, bulk CMOS to 50n and below [1,138]. If the present understanding of the barriers and problems to scaling planar, bulk CMOS below 50nm is correct, then it is expected that a dramatic shift to fully depleted SOI CMOS will occur in the [61,70,71] 2006-2008 timeframe.…”

“…For example, "short channel effects" (SCE) are typically suppressed more effectively in SOI CMOS devices than in bulk CMOS, and SOI CMOS devices typically have lower subthreshold leakage ("off current") and higher saturation current ("on current") than bulk CMOS counterparts [5,101,18,37]. Consequently, the SOI CMOS circuits typically demonstrate higher speed performance and lower power dissipation than bulk or epitaxial CMOS.…”

“…Consequently, the SOI CMOS circuits typically demonstrate higher speed performance and lower power dissipation than bulk or epitaxial CMOS. Also, the SOI CMOS device exhibits several parasitic phenomena that are not typically observed in the bulk or epitaxial CMOS device [5,6,132].…”

“…The point is that the SOI CMOS transistor is different than the bulk CMOS transistor and these differences must be reflected in the simulators employed to design devices and circuits for CMOS ICs [5,6,133]. These effects arise in SOI devices because the device is thermally insulated from the substrate by the buried oxide (BOX).…”

“…There are significant differences in partially depleted and fully depleted SOI CMOS transistors [5,134]. For example, the threshold voltage of the fully depleted (FD) device is very sensitive to the silicon surface film thickness.…”