FSM-controlled architectures for linear invasion

Abstract

Abstract-Invasive computing is a novel concept in multiprocessor architecture and programming. Invasion will become an important step towards self-organizing behavior which will be needed in the next generation of massively parallel MPSoCs with unrivaled performance and resource efficiency numbers as one of the main challenges for MPSoC apart from their programming. In this paper we introduce and model a finite state machine for controlling the invasive process in different architectural granularities. The applicability of our FSM is tested in case studies for a reconfigurable MPSoC platform and a fine-grained platform. The results show substantial flexibility gains with only marginal additional hardware cost.

Decentralized dynamic resource management support for massively parallel processor arrays

“…In previous work [14], a basic FSM-based invasion controller was proposed. This controller was targeting linear arrays of PEs and was able to acquire one PE in every cycle during the invasion phase.…”

Distributed Resource Reservation in Massively Parallel Processor Arrays

“…The implementation of such a controller may vary according to the architectural requirements and constraints from a simple FSM-based implementation for arealimited architectures, as introduced in [6], to a programmable co-processor. Here, despite of the work in [6] where the controller was designed just for one-dimensional processor arrays, we have extended the controller to support exploration and reservation of a linear chain of connected PEs on general multi-dimensional architectures. The next section proposes different approaches for gathering resource explorations and for informing a configuration loader for infecting sets of captured PEs.…”

“…We call this information a "claim". In [6], a simple integer is incremented and rippled back to the master PE as the number of captured PEs after a successful exploration process. This mechanism could work perfectly for a simple linear array of processing elements, but for more complex architectures, like two dimensional coarse-grained reconfigurable arrays (CGRAs) [4], [7], such results should reflect not only the amount of captured PEs, but also their locations.…”