Full chip false timing path identification: applications to the PowerPC/sup TM/ microprocessors

Abstract

Static timing analysis sets the industry standard in the design methodology of high speea7performance microprocessors to determine whether timing requirements have been met. Unfortunately, not all the paths identQied using such analysis can be sensitized. This leads to a pessimistic estimation of the processor speed. Also, no amount of engineering eflort spent on optimizing such paths can improve the timing performance of the chip. In the past, we demonstrated initial results of how ATPG techniques can be used to identifi false paths eficiently [l]. Due to the gap between the physical design on which the static timing analysis of the chip is bused and the test view on which the ATPG techniques are applied to identifi false paths, in many cases only sections of some of the paths in the full-chip were analyzed in our initial results. In this papec we will fully analyze all the timing paths using the ATPG techniques, thus overcoming the gap between the testing and timing analysis techniques. This enables us to do false path identification at the full-chip level of the circuit. Results of applying our technique to the second generation G4 PowerPCTM will be presented.