Full-wafer fabrication by nanostencil lithography of micro/nanomechanical mass sensors monolithically integrated with CMOS

Abstract

Wafer-scale nanostencil lithography (nSL) is used to define several types of silicon mechanical resonators, whose dimensions range from 20 µm down to 200 nm, monolithically integrated with CMOS circuits. We demonstrate the simultaneous patterning by nSL of ∼2000 nanodevices per wafer by post-processing standard CMOS substrates using one single metal evaporation, pattern transfer to silicon and subsequent etch of the sacrificial layer. Resonance frequencies in the MHz range were measured in air and vacuum. As proof-of-concept towards an application as high performance sensors, CMOS integrated nano/micromechanical resonators are successfully implemented as ultra-sensitive areal mass sensors. These devices demonstrate the ability to monitor the deposition of gold layers whose average thickness is smaller than a monolayer. Their areal mass sensitivity is in the range of 10(-11) g cm(-2) Hz(-1), and their thickness resolution corresponds to approximately a thousandth of a monolayer.

In-plane nanoelectromechanical resonators based on silicon nanowire piezoresistive detection

“…For long time constant, the minimum Allan deviation reaches 6 × 10 −7 . This value is quite a classical one, reported in many papers (see [3,9,22] for example), and might be considered as the experimental limit.…”

“…V out is proportional to δ R/R according to equation (3). The SNR for the semiconducting gauge over the SNR of the metallic gauge can be simply expressed by…”

“…A lot of effort has been devoted to developing new transduction and background reduction [6]. A variety of NEMS detection techniques, such as capacitive [3,7,8], magnetomotive [9], piezoresistive [10,11] and field-emission [4,12] transduction, have been proposed. The magnetomotive approach typically requires large magnetic fields (2-8 T) and is thus not suitable for integrated applications.…”

“…Moreover, this technique uses bottom-up approach that is hardly compatible with large scale integration (VLSI) process. A piezoresistive detection scheme offers great 3 Present address: Stanford University, Stanford, CA 94305-4070, USA. potential compared to a capacitive one especially for high resonant frequency measurements [10,13].…”

Double-gate pentacene thin-film transistor with improved control in sub-threshold region

“…In view of further miniaturization and process improvements we adopted a previously reported aligned stencil lithography process [5,6] as a clean, resistless, in-vacuum patterning technique for organic electronic devices on plastic substrates. A typical stencil is composed of low-stress silicon nitride (SiN) membranes, which contain design-specific micro-apertures.…”