Fully aligned via integration for extendibility of interconnects to beyond the 7 nm node

Briggs, Benjamin D.; Peethala, C. B.; Rath, D.L.; Lee, J.; Nguyen, S.; LiCausi, Nicholas; McLaughlin, P.; You, Heung Cheol; Sil, Devika; Lanzillo, Nicholas A.; Huang, H. Y.; Patlolla, R.; Haigh, T.; Xu, Yaxing; Park, C.; Kerber, P.; Shobha, H.; Kim, Y.; Demarest, J.; Li, J.; Lian, Guoda; Ali, Muhammad Zeshan; Le, Chuck; Ryan, E. Todd; Clevenger, L. A.; Canaperi, D.; Standaert, T.; Bonilla, G.; Huang, E.

doi:10.1109/iedm.2017.8268388

Cited by 16 publications

(17 citation statements)

References 3 publications

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Section: Motivation and Applications For Area-selective Depositionmentioning

confidence: 99%

“…The fully self-aligned via (FSAV) process flow has recently been proposed in order to provide an additional edge placement error (EPE) margin for via alignment from one level to another during interconnect formation. 122 The ASD enhanced FSAV process flow, Figure 11, provides significant advantages over the originally proposed process flow by avoiding the need for a difficult metal recess etch to form the topography needed for self-alignment at the bottom of the via. 115 In this process flow a selective DoD process is used to create a dielectric scaffold that prevents the vias from coming too close to the neighboring metal features, resulting in a greater process margin for EPE during via formation.…”

Section: Systems-level Issues In Asd: Featurementioning

confidence: 99%

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Area-Selective Deposition: Fundamentals, Applications, and Future Outlook

Parsons

Clark²

2020

Chem. Mater.

236

276

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This review provides an overview of area-selective thin film deposition (ASD) with a primary focus on vapor-phase thin film formation via chemical vapor deposition (CVD) and atomic layer deposition (ALD). Areaselective deposition has been successfully implemented in microelectronic processes, but most approaches to date rely on high-temperature reactions to achieve the desired substrate sensitivity. Continued size and performance scaling of microelectronics, as well as new materials, patterning methods, and device fabrication schemes are seeking solutions for new low-temperature (<400 °C) ASD methods for dielectrics, metals, and organic thin films. To provide an overview of the ASD field, this article critically reviews key challenges that must be overcome for ASD to be successful in microelectronics and other fields, including descriptions of current process application needs. We provide an overview of basic mechanisms in film nucleation during CVD and ALD and summarize current known ASD approaches for semiconductors, metals, dielectrics, and organic materials. For a few key materials, selectivity is quantitatively compared for different reaction precursors, giving important insight into needs for favorable reactant and reaction design. We summarize current limitations of ASD and future opportunities that could be achieved using advanced bottom-up atomic scale processes.

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Section: Motivation and Applications For Area-selective Depositionmentioning

confidence: 99%

Section: Systems-level Issues In Asd: Featurementioning

confidence: 99%

Area-Selective Deposition: Fundamentals, Applications, and Future Outlook

Parsons

Clark²

2020

Chem. Mater.

236

276

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“…To avoid shorting caused by edge placement errors, a fully self-aligned via (FSAV) fabrication design has been highlighted. 1 Introducing topographical height differences on metal/low dielectric constant (low-k) material patterns before the deposition of thin films in the next layer is one strategy to realize the FSAV, which works by increasing the spacing between vias and metal lines. 2,3 To create topography for FSAV schemes, both metal recess etching and area-selective deposition (ASD) have been proposed as possible solutions.…”

Section: ■ Introductionmentioning

confidence: 99%

“…2,3 To create topography for FSAV schemes, both metal recess etching and area-selective deposition (ASD) have been proposed as possible solutions. 1,2,4 Although metal recessing has been widely adopted in industry, this approach has disadvantages such as multiplex processes, poor uniformity, and large surface roughness. Alternatively, ASD is preferred, given its precise thickness control and excellent surface uniformity.…”

Section: ■ Introductionmentioning

confidence: 99%

“…To avoid shorting caused by edge placement errors, a fully self-aligned via (FSAV) fabrication design has been highlighted . Introducing topographical height differences on metal/low dielectric constant (low- k ) material patterns before the deposition of thin films in the next layer is one strategy to realize the FSAV, which works by increasing the spacing between vias and metal lines. , To create topography for FSAV schemes, both metal recess etching and area-selective deposition (ASD) have been proposed as possible solutions. ,, Although metal recessing has been widely adopted in industry, this approach has disadvantages such as multiplex processes, poor uniformity, and large surface roughness. Alternatively, ASD is preferred, given its precise thickness control and excellent surface uniformity.…”

Section: Introductionmentioning

confidence: 99%

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Area-Selective Molecular Layer Deposition of a Silicon Oxycarbide Low-k Dielectric

Bobb-Semple

et al. 2021

Chem. Mater.

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Area-selective deposition (ASD) of low-k materials is desired in back-end-of-line processes for fabricating nanopatterns such as fully self-aligned vias. However, the high temperature and/or aggressive coreactants used in conventional low-k material deposition have limited the application of the organic inhibitors used in ASD. Here, we report a strategy to selectively deposit low-k methylene-bridged silicon oxycarbide (SiOC) thin films on metal/dielectric patterns by combining growth using molecular layer deposition (MLD) and inhibition using self-assembled monolayers (SAMs). By using bis (trichlorosilyl)-methane and water as a precursor and coreactant, respectively, SiOC thin films with a dielectric constant of 3.6–3.8 are deposited at 40 °C and at a growth rate of 1.5 Å/cycle. We demonstrate area-selective MLD of this SiOC material for up to 30 cycles (equiv. 4.5 nm) on SiO2 vs Cu using a dodecanethiol SAM to block growth on Cu, and up to 70 cycles (equiv. 10 nm) on SiO2 vs Al using an octadecylphosphonic acid SAM to block growth on native oxide-covered Al. Positive and negative pattern transfer of SiOC films on a Cu/Al2O3 pattern is exhibited as a proof of concept. Moreover, because the Cu substrates are contaminated by HCl which is generated as a byproduct in the MLD process, we develop a mild post-treatment method using ethanol to remove chlorine residues.

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