Fully digital fast transient phase-locked digital LDO-embedded-MDLL for DVFS applications

Akram, Muhammad Abrar; Hwang, Inseok

doi:10.1007/s10470-017-1028-x

Cited by 5 publications

(4 citation statements)

References 11 publications

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“…Thus, the clock intrinsically adapts to the voltage (V REG ) and temperature variations while variations in the load circuit's critical path delays are compensated. As a result, the timing margins are maintained nearly constant in the implemented FR-DLDO [63]. However, the critical path modeling of the TRO is totally load-circuit-specific.…”

Section: Proposed Heterogeneous Pdn Using Frequency-referenced Dldosmentioning

confidence: 99%

“…But its current driving capability is also minimal at 6 mA. To overcome these limitations of the FR-DLDOs [65], [69], a fast-transient FR-DLDO with a large current-driving capacity and wide regulation range is presented in the next section [63]. The FR-DLDO achieves a faster transient response time due to its transient-boost control.…”

Section: Proposed Heterogeneous Pdn Using Frequency-referenced Dldosmentioning

confidence: 99%

“…Fig. 15 shows a block diagram of the implemented FR-DLDO (presented in [63]) for the proposed heterogeneous PDN. The FR-DLDO generates both V REG and F REG by using a single regulation loop with a TRO, as shown in Fig.…”

Section: Proposed Heterogeneous Pdn Using Frequency-referenced Dldosmentioning

confidence: 99%

“…To enhance the load transient response and reduce the voltage undershoot (∆ V REG ) for load current step changes, a transient-boost control was proposed [63]. Its circuit diagram is shown in Fig.…”

Section: ) Transient-boost Controlmentioning

confidence: 99%

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Power Delivery Networks for Embedded Mobile SoCs: Architectural Advancements and Design Challenges

Akram

Hwang

2021

IEEE Access

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Conventional power delivery networks (PDNs) and power management techniques using off-chip power converters with bulky passive components cannot meet the ever-evolving power delivery requirements of high-performance modern system-on-chips (SoCs). In SoCs, heterogeneous components, including multi-core processors and mixed-signals peripheral circuits, require state-of-the-art PDNs to provide high-quality power-on-demand with minimum latency, simultaneously achieving the small-factor, high conversion efficiency, and minimum current consumption. To satisfy these power delivery requirements, various PDNs have been developed over the past decades, such as the conventional architectures using off-chip power converters, architectures using in-package power converters and fully-integrated power converters, and heterogeneous architectures (off-chip power converters and on-chip regulators). This paper reviews these architectural advancements of the PDNs and their advantages and limitations, which leads us to discuss a heterogeneous PDN structure consisting of a highly efficient off-chip switching-mode power converter and multiple highly precise small linear regulators integrated on chip at point-of-load locations. The heterogeneous PDN has been proved one of the most suitable architectures to achieve high-quality finegrained on-chip power delivery and management in SoCs. This paper also discusses unified voltage and frequency regulators (UVFRs), which support dynamic-variation-aware dynamic voltage and frequency scaling (DVFS) for fine-grained power management in multi-core processors. Based on the UVFR, we propose a modified heterogeneous PDN using frequency-referenced digital low-dropout regulators (FR-DLDOs) for more efficient DVFS, eliminating the need for band-gap circuits to provide reference voltages. As an exemplary implementation of FR-DLDO for this PDN, we present an FR-DLDO with a transientboost control, which accelerates the transient response. The transient-boost control is activated dynamically only when an abrupt change happens out of the steady state. The implemented FR-DLDO fabricated in a 40-nm CMOS process outperforms other FR-DLDOs in the figure-of-merit and peak power efficiency while driving 40 mA of load current. INDEX TERMS Power delivery network (PDN); fine-grained power management; dynamic-voltage and frequency scaling (DVFS); dynamic-voltage scaling (DVS); low-dropout regulator (LDO); digital LDO; unified-voltage and frequency regulator (UVFR); frequency-referenced digital LDO (FR-DLDO); transientboost control.

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Section: Proposed Heterogeneous Pdn Using Frequency-referenced Dldosmentioning

confidence: 99%

Section: Proposed Heterogeneous Pdn Using Frequency-referenced Dldosmentioning

confidence: 99%

Section: Proposed Heterogeneous Pdn Using Frequency-referenced Dldosmentioning

confidence: 99%

Section: ) Transient-boost Controlmentioning

confidence: 99%

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Power Delivery Networks for Embedded Mobile SoCs: Architectural Advancements and Design Challenges

Akram

Hwang

2021

IEEE Access

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All digital duty-cycle corrector for integrated phase noise improvement in phase-locked loop

Akram

Kim

Bae

et al. 2019

Analog Integr Circ Sig Process

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Architectural Advancement of Digital Low-Dropout Regulators

Akram

Hwang

2020

IEEE Access

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Digital Low-dropout (DLDO) regulators have been widely utilised for highly-efficient finegrained power delivery and management in system-on-chips (SoCs) due to their process scalability, ease of integration, and low-voltage operation. However, conventional DLDOs suffer gravely from the power-speed tradeoff, which arises from the use of sampling clocks. To obtain reasonable performance in the undershoot and recovery during load transient states, a large output capacitor is inevitably required in these DLDOs. Moreover, they inherently involve large steady-state voltage ripples and poor power-supply rejection (PSR). These limitations of synchronous DLDOs and their counter measures are thoroughly discussed in this paper. Various design strategies of major building blocks, i.e. comparators and power transistor arrays, are explained in detail with examples. Architectural advances are also expounded including state-of-the-art DLDO architectures such as clock-boosted synchronous, analog-assisted synchronous, asynchornous, eventdriven, and hybrid DLDOs. These state-of-the-art DLDOs do not only address the power-speed tradeoff and achieve fast load transient responses, but also can eliminate the use of an output capacitor in some cases. Moreover, some hybrid DLDOs successfully removed the steady state ripples and achieve high PSR. All of these DLDO are compared on basis of their performance metrics and figure-of-merits (FOMs).

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Fully digital fast transient phase-locked digital LDO-embedded-MDLL for DVFS applications

Cited by 5 publications

References 11 publications

Power Delivery Networks for Embedded Mobile SoCs: Architectural Advancements and Design Challenges

Power Delivery Networks for Embedded Mobile SoCs: Architectural Advancements and Design Challenges

All digital duty-cycle corrector for integrated phase noise improvement in phase-locked loop

Architectural Advancement of Digital Low-Dropout Regulators

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