Fully Integrated 1.8 V Output 300 mA Load LDO with Fast Transient Response

Abstract

Based on an 0.18 μm process, this paper proposes a fully integrated 1.8 V output 300 mA load low-dropout linear regulator (LDO) with a fast transient response. By inserting a transient-enhanced biased Class AB super source follower at the gate of the output power transistor, this LDO can quickly adjust the gate voltage of the power transistor without additional power consumption. By adding an active capacitor circuit composed of a fast comparator with offset voltage at the output point, this LDO can quickly charge/discharge the transient current and accelerate the transient response without reducing the circuit stability. Simulation results show that the proposed LDO has an output voltage of 1.8 V, when the input voltage is 2 V to 5 V while consuming 66.4 μA of quiescent current. The proposed capless LDO has a 1.94 µV/mA load regulation, a 0.55 mV/V linear regulation, and a −60 dB@1kHz power supply rejection. When the load current steps from 3 mA to 300 mA in 300 ns, the LDO settles in 400 ns with an overshoot and undershoot of 67 mV and 86 mV, respectively.

A Double-Edge-Triggered Digital LDO with Built-In Adaptive VCO Clock for Fast Transient Response and Low Power Consumption

“…Moreover, even though the power of the AVC is included, the quiescent current of the entire DLDO is still very low, resulting in the two FoMs. Meanwhile, we provide a comparison of the related simulation results with the previous publications [1,2,23,24] in Table 4 regarding the analog LDOs in electronics. It can be seen from Table 4 that the static power consumption of the recent analog LDOs is comparable to that of the proposed DLDO.…”

“…In Internet of Things (IoT) and system-on-chip (SoC) application scenarios, energyefficient fine-grained power management systems are indispensable for self-power wireless sensors due to the limited power capability of the supply and energy harvester. At high supply voltages (e.g., 1.2 V and above), analog low-dropout regulators (LDOs) can regulate a constant voltage for analog and RF modules due to their excellent noise performance and high PSRR characteristics, which maximize the performance and energy efficiency [1,2]. With CMOS process scaling, the intrinsic gain of the transistors is smaller, leading to an analog circuit accuracy reduction.…”

Design of high-reliability LDO regulator incorporated with SCR based ESD protection circuit using transient switch structure

“…Power management integrated circuit is essential for modern battery-powered devices that combine low power consumption and high performance. In particular, LDO regulators provide stable and accurate output voltages, and the design of LDO regulators is becoming increasingly important for space saving and long-term reliability, requiring sophisticated design of the internal system [1,2,3,4,5,6,7]. As shown in Fig 1, incorporated with ESD protection circuit in the LDO regulator, the durability and reliability of electronic devices are not only significantly improved, but also the design space can be saved by using SCR-based ESD protection circuit compared to large area diodes, thereby ensuring price competitiveness [8,9,10,11,12].…”

Design of Destruction Protection and Sustainability Low-Dropout Regulator Using an Electrostatic Discharge Protection Circuit

“…Such an ESD protection circuit must be embedded to ensure the reliability and lifespan of the IC, such as those used in LDO regulators. Also, the LDO regulators presented in the previous papers do not have an ESD protection circuit [2][3][4]. If each circuit is individually designed and operated, this is not a problem.…”