Fully X-tolerant, very high scan compression

Wohl, P.; Waicukauski, J.A.; Neuveux, F.; Gizdarski, Emil

doi:10.1145/1837274.1837366

Cited by 46 publications

(17 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The decompressors in these cases have a relatively low encoding capacity, and thus ATPG has to compensate for that. The two-phase methods comprise both combinational solutions [2], [34], and LFSR coding [25], which subsequently evolved first into static LFSR reseeding [15], [17], [20], [26], [48], [53], [54], and then into dynamic LFSR reseeding [1], [35]. In particular, the Embedded Deterministic Test (EDT) -a distinct form of dynamic reseeding -has gained broad acceptance as a reliable industrial solution [36].…”

Section: A Prior Workmentioning

confidence: 99%

Isometric Test Data Compression

Kumar

Kassab

Moghaddam

et al. 2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

View full text Add to dashboard Cite

The paper introduces a novel test data compression scheme, which is primarily devised for low power test applications. It is based on a fundamental observation that in addition to low test cube fill rates, a very few specified bits, necessary to detect a fault, are actually irreplaceable, whereas the remaining ones can be placed in alternative locations (scan cells). The former assignments are used to create residual test cubes and, subsequently, test templates. They control a power-aware decompressor and guide ATPG to produce highly compressible test patterns through finding alternative assignments. The proposed approach reduces, in a user-controlled manner, scan shift-in switching rates with minimal hardware modifications. It also elevates compression ratios to values typically unachievable through conventional low-power reseeding-based solutions. Experimental results obtained for large industrial designs illustrate feasibility of the proposed test scheme and are reported herein.Index Terms-Design for testability, embedded deterministic test, low power test, scan-based designs, test compression.

show abstract

Section: A Prior Workmentioning

confidence: 99%

Isometric Test Data Compression

Kumar

Kassab

Moghaddam

et al. 2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

View full text Add to dashboard Cite

show abstract

“…The first element, test application time, is dominated by scan test. Various scan compression methods have been developed to reduce test application time [2], [3], [4]. Scan cells are configured in multiple short internal scan chains connected between on-chip compressor / decompressor (CODEC) structures; the ATE supplies data which is decoded into care bits, unknown values (X) management and expected responses.…”

Section: Introductionmentioning

confidence: 99%

Achieving extreme scan compression for SoC Designs

Wohl

Waicukauski

Colburn³

et al. 2014

2014 International Test Conference

Self Cite

View full text Add to dashboard Cite

High volume testing of complex System on Chip (SoC) designs at reasonable test cost requires high test data and test time compression. We present a multilevel scan compression architecture that combines a flexible test compression core with an efficient dynamic broadcast structure and a high speed data access technique. Full X-tolerance, power-aware scan shift and diagnosis are supported through the entire architecture. We present a flow for assembling the various components that limits the impact on area and timing by minimizing test signals and improving modularity of the inserted design-for-test (DFT) structures. These techniques provided a reduction of 600x in test data volume and over 2300x in test time on large Graphics Processor Units (GPU) designs.

show abstract

“…in embedded deterministic test or built-in self test), special handling of X-values in the compactor is necessary to avoid compromising the response signature. X-tolerant compactors [2], X-canceling time compactors [3] or structures for X-masking [4] can be used.…”

Section: Introductionmentioning

confidence: 99%

Accurate Multi-cycle ATPG in Presence of X-Values

Erb

Kochte

Sauer

et al. 2013

2013 22nd Asian Test Symposium

View full text Add to dashboard Cite

Unknown (X) values in a circuit impair test quality and increase test costs. Classical n-valued algorithms for fault simulation and ATPG, which typically use a three-or four-valued logic for the good and faulty circuit, are in principle pessimistic in presence of X-values and cannot accurately compute the achievable fault coverage.In partial scan or pipelined circuits, X-values originate in non-scan flip-flops. These circuits are tested using multi-cycle tests. Here we present multi-cycle test generation techniques for circuits with X-values due to partial scan or other X-sources. The proposed techniques have been integrated into a multi-cycle ATPG framework which employs formal Boolean and quantified Boolean (QBF) satisfiability techniques to compute the possible signal states in the circuit accurately. Efficient encoding of the problem instance ensures reasonable runtimes.We show that in presence of X-values, the detection of stuck-at faults requires not only exact formal reasoning in a single cycle, but especially the consideration of multiple cycles for excitation of the fault site as well as propagation and controlled reconvergence of fault effects.For the first time, accurate deterministic ATPG for multi-cycle test application is supported for stuck-at faults. Experiments on ISCAS'89 and industrial circuits with X-sources show that this new approach increases the fault coverage considerably.

show abstract

Fully X-tolerant, very high scan compression

Cited by 46 publications

References 7 publications

Isometric Test Data Compression

Isometric Test Data Compression

Achieving extreme scan compression for SoC Designs

Accurate Multi-cycle ATPG in Presence of X-Values

Contact Info

Product

Resources

About