Functional Constraint Extraction From Register Transfer Level for ATPG

Hobeika, Christelle; Thibeault, Claude; Boland, Jean-François

doi:10.1109/tvlsi.2014.2309439

Cited by 2 publications

(1 citation statement)

References 19 publications

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“…They then present a method of effectively using this statistical information to guide the ATPG efforts. [70,71] an RTL illegal state extraction methodology based on code parsing and parsing expression grammar (PEG). The extracted values help building functional constraints that are forced during ATPG process in order to generate pseudo-functional test patterns.…”

Section: Thaker Et Al Use Inmentioning

confidence: 99%

A Novel RTL ATPG Model Based on Gate Inherent Faults (GIF-PO) of Complex Gates

Strauch¹

2016

Preprint

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This paper starts with a comprehensive survey on RTL ATPG. It then proposes a novel RTL ATPG model based on "Gate Inherent Faults" (GIF). These GIF are extracted from each complex gate (adder, case-statement, etc.) of the RTL source code individually. They are related to the internal logic paths of a complex gate. They are not related to any net/signal in the RTL design. It is observed, that when all GIF on RTL are covered (100%) and the same stimulus is applied, then all gate level stuck-at faults of the netlist are covered (100%) as well. The proposed RTL ATPG model is therefore synthesis independent. This is shown on ITC'99 testcases. The applied semi-automatic test pattern generation process is based on functional simulation.

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Section: Thaker Et Al Use Inmentioning

confidence: 99%

A Novel RTL ATPG Model Based on Gate Inherent Faults (GIF-PO) of Complex Gates

Strauch¹

2016

Preprint

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Towards an Automatic Test Generation Method for Systems of Systems Based on Fault Injection and Model-Based Systems Engineering

Tian

Jing

2022

Applied Sciences

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The emergence and development of systems of systems (SoSs) have expanded the complexity and adaptability of systems engineering. Due to the heterogeneity of its constituent systems, designing and analyzing an SoS faces enormous challenges. Therefore, the verification of an SoS is important in its design phase. However, related methods and techniques are still in the preliminary research state, mainly for requirements verification and system verification, and a lack of efforts in design verification for SoSs. Aiming to provide the ability to detect hazardous states at the design phase, we worked on a novel method for automatically generating test cases for model verification in SoSs. Considering the characteristics of SoSs, the method adopts fault injection and model-based system engineering as the foundations to extend the automated generation capability of test cases. This paper proposes an automatic test generation (ATG) method for an SoS based on fault injection and model-based systems engineering (MBSE). It is meant to generate test cases that can be used to check the effectiveness of fault detection or identification in SoSs and for the effective testing of their constituent systems (CSs). This paper discusses scenario generation and ATG in linear temporal logic and designs an algorithm to generate traces as test suites, taking into account the constraints of the models. By establishing a concept alignment example (CAE) as the experimental use case, three test scenarios are generated automatically, showing that the use of the proposed ATG method provides a reasonable hazardous detection capability for verification in SoS design. The main contributions of the paper are (1) the description of the proposed two-phase ATG approach with fault-centric modeling activities and generation-related activities; (2) the explanation of the designed ATG algorithm at both high and low levels; and (3) the discussion of the experiment in an emergency response CAE with three generated test scenarios.

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Functional Constraint Extraction From Register Transfer Level for ATPG

Cited by 2 publications

References 19 publications

A Novel RTL ATPG Model Based on Gate Inherent Faults (GIF-PO) of Complex Gates

A Novel RTL ATPG Model Based on Gate Inherent Faults (GIF-PO) of Complex Gates

Towards an Automatic Test Generation Method for Systems of Systems Based on Fault Injection and Model-Based Systems Engineering

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