Functional Test Environment for Time-Triggered Control Systems in Complex MPSoCs Using GALI

Seyyedi, Razi; Schreiner, Sören; Fakih, Maher; Grüttner, Kim; Nebel, Wolfgang

doi:10.1109/dsd.2018.00010

Cited by 3 publications

(3 citation statements)

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“…• Monitoring partition to observe concept in [11][12][13] power rails and temperature on the PCB • Validation of low-power methods and RT schedules on the virtual platform [11,12] Schedulability of hard real-time Yes, main contribution • Low-power savings up to 37% on hard applications under power management real-time industrial use cases Certifiability of power and temperature No, covered in [2] • Safety compliant low-power architecture management techniques with 3rd party expert assessment…”

Section: Requirement Covered In This Article Main Result(s)mentioning

confidence: 99%

“…The SAFEPOWER (http://www.safepower-project.eu) project aims at providing a reference architecture, which demonstrates the applicability of low-power techniques for mixed-criticality systems [10]. In our previous publications [2,[10][11][12][13], we have addressed the fulfilment of several indispensable requirements by our suggested SAFEPOWER architecture to enable the usage of low-power management techniques in mixed-criticality systems. Table 1 depicts our prior contributions and positions our current work with respect to them.…”

Section: Introductionmentioning

confidence: 99%

“…Execution control: This is the deterministic simulation and full control of all processing elements. In the scope of the SAFEPOWER project, this was extended to support the simulation of time-triggered schedules (see [12]). • Unified debug environment: This allows the simultaneous debugging of all application code executing on the processors in conjunction with access to the peripheral models (programmers view and behaviour) and shared resources, for example memory.…”

mentioning

confidence: 99%

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Experimental Evaluation of SAFEPOWER Architecture for Safe and Power-Efficient Mixed-Criticality Systems

Fakih

Grüttner

Schreiner

et al. 2019

JLPEA

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With the ever-increasing industrial demand for bigger, faster and more efficient systems, a growing number of cores is integrated on a single chip. Additionally, their performance is further maximized by simultaneously executing as many processes as possible. Even in safety-critical domains like railway and avionics, multicore processors are introduced, but under strict certification regulations. As the number of cores is continuously expanding, the importance of cost-effectiveness grows. One way to increase the cost-efficiency of such a System on Chip (SoC) is to enhance the way the SoC handles its power consumption. By increasing the power efficiency, the reliability of the SoC is raised because the lifetime of the battery lengthens. Secondly, by having less energy consumed, the emitted heat is reduced in the SoC, which translates into fewer cooling devices. Though energy efficiency has been thoroughly researched, there is no application of those power-saving methods in safety-critical domains yet. The EU project SAFEPOWER (Safe and secure mixed-criticality systems with low power requirements) targets this research gap and aims to introduce certifiable methods to improve the power efficiency of mixed-criticality systems. This article provides an overview of the SAFEPOWER reference architecture for low-power mixed-criticality systems, which is the most important outcome of the project. Furthermore, the application of this reference architecture in novel railway interlocking and flight controller avionic systems was demonstrated, showing the capability to achieve power savings up to 37%, while still guaranteeing time-triggered task execution and time-triggered NoC-based communication.

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