Functional test of small-delay faults using SAT and Craig interpolation

Sauer, Matthias; Kupferschmid, Stefan; Czutro, Alexander; Polian, Ilia; Reddy, S.M.; Becker, Bernd

doi:10.1109/test.2012.6401550

Cited by 25 publications

(14 citation statements)

References 32 publications

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“…• One of PHAETON's design goals has been to simplify the integration with applications making use of the versatile requirement system and hence enable sensitizable path-based concepts in novel areas beyond the classical scenario of small-delay fault testing, e.g., the functional detection of small delay faults through longest paths in sequential circuits [68], [69]. Thereby, optimization and compaction plays a role, as well as proving untestability by transfering methods known from the formal verification area [70] to the test area.…”

Section: Further Developments and Current Trendsmentioning

confidence: 99%

Recent advances in SAT-based ATPG: Non-standard fault models, multi constraints and optimization

Becker

Drechsler

Eggersglüß

et al. 2014

2014 9th IEEE International Conference on Design &Amp; Technology of Integrated Systems in Nanoscale Era (DTIS)

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Abstract-It is well-known that in principle automatic test pattern generation (ATPG) can be solved by transforming the circuit and the fault considered into a Boolean satisfiability (SAT) instance and then calling a so-called SAT solver to compute a test. More recently, the potential of SAT-based ATPG has been significantly extended. In this paper, we first provide introductory knowledge on SAT-based ATPG and then report on latest developments enabling applications far beyond classical ATPG.

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Section: Further Developments and Current Trendsmentioning

confidence: 99%

Recent advances in SAT-based ATPG: Non-standard fault models, multi constraints and optimization

Becker

Drechsler

Eggersglüß

et al. 2014

2014 9th IEEE International Conference on Design &Amp; Technology of Integrated Systems in Nanoscale Era (DTIS)

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“…Deterministic sequential test generation procedures, most recently Sauer et al [2012], have a high computational complexity. Incorporating test compaction heuristics into the sequential test generation procedure increases its computational complexity further.…”

Section: Introductionmentioning

confidence: 99%

A Generalized Definition of Unnecessary Test Vectors in Functional Test Sequences

Pomeranz

2015

ACM Trans. Des. Autom. Electron. Syst.

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A class of static test compaction procedures for functional test sequences is based on the omission of unnecessary test vectors. According to the definition used by these procedures, a test vector is unnecessary if all the target faults continue to be detected after it is omitted. This article introduces a more general definition of unnecessary test vectors that allows additional ones to be omitted. According to this definition, a test vector is unnecessary if every target fault can be detected by a sequence that is obtained after omitting the vector, and possibly other vectors. The article develops a procedure for omitting test vectors based on this definition and discusses its effects on the storage requirements and test application time. ACM Reference Format:Irith Pomeranz. 2015. A generalized definition of unnecessary test vectors in functional test sequences. ACM Trans.

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“…Although the first guidelines to manually perform this task go back to several decades ago [3], techniques to automate are still not developed enough and several research efforts are on-going, targeting both stuck-at [4] and delay faults [5]. In [6] a technique was recently introduced to generate test patterns for small-delay faults, whose importance to achieve high defect coverage has been largely recognized in industry [7]. The method was developed resorting to Bounded Model Checking (BMC) and its effectiveness was validated on the ITC 99 benchmark circuits [8].…”

Section: Introductionmentioning

confidence: 99%

An effective approach to automatic functional processor test generation for small-delay faults

Riefert

Ciganda

Sauer

et al. 2014

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2014

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Functional microprocessor test methods provide several advantages compared to DFT approaches, like reduced chip cost and at-speed execution. However, the automatic generation of functional test patterns is an open issue.In this work we present an approach for the automatic generation of functional microprocessor test sequences for small-delay faults based on Bounded Model Checking. We utilize an ATPG framework for small-delay faults in sequential, non-scan circuits and propose a method for constraining the input space for generating functional test sequences (i.e., test programs). We verify our approach by evaluating the miniMIPS microprocessor. In our experiments we were able to reach over 97 % fault efficiency.To the best of our knowledge, this is the first fully automated approach to functional microprocessor test for small-delay faults.

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Functional test of small-delay faults using SAT and Craig interpolation

Cited by 25 publications

References 32 publications

Recent advances in SAT-based ATPG: Non-standard fault models, multi constraints and optimization

Recent advances in SAT-based ATPG: Non-standard fault models, multi constraints and optimization

A Generalized Definition of Unnecessary Test Vectors in Functional Test Sequences

An effective approach to automatic functional processor test generation for small-delay faults

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