Functional verification of large ASICs

Full-system emulation and prototyping is now being used widely in the industry for System-on-Chip (SoC) verification. Emulation/ prototyping platforms run tests in a fraction of time compared to the traditional simulation based verification. However, unlike simulation, they do not provide visibility into the hardware design source code. As a result, they fail to provide any information about code coverage achieved, which is an important metric to measure the completeness of the verification process.In this paper, we present a novel technique to extract code coverage from emulation/prototyping platforms. Through analysis of the source code for the hardware design, we relate the evaluation of branch conditions to other statements in the code. Evaluation of the branch conditions is recorded using additional logic during emulation, and mapped back to the code to obtain coverage information. We apply our technique to an industrial system, and show that it can efficiently provide code coverage statistics that are faithful to the coverage obtained from simulation. We also perform experiments on the publicly available OpenRISC processor and demonstrate similar results.

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“…(4) s belongs to the same basic block as a statement s ′ from (1) or (2) and consequently execution of s ′ ensures the execution of s.…”

Section: Estimating Coverage Of Branch Conditionsmentioning

confidence: 99%

“…Today, verification consumes a considerable amount of resources in the System-on-Chip (SoC) development life cycle [1]. With increasingly complex SoCs and shorter times-to-market, over 70% of the engineering resources and time are spent on various forms of verification alone.…”

Section: Introductionmentioning

confidence: 99%

Using static analysis for coverage extraction fromemulation/prototyping platforms

Athavale

Hertz

Jetly

et al. 2012

Proceedings of the Eighth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis

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“…The conventional VHDL-based design methodology is very time consuming and difficult to explore the design space extensively [15]. In this paper, a Catapult C High Level Synthesis (HLS) design methodology is proposed to explore design space extensively using layered parallelism and pipelining [9].…”

Section: Introductionmentioning

confidence: 99%

A Low Complexity and Low Power SoC Design Architecture for Adaptive MAI Suppression in CDMA Systems

Guo

Cavallaro

2006

J VLSI Sign Process Syst Sign Image Video Technol

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In this paper, we propose a reduced complexity and power efficient System-on-Chip (SoC) architecture for adaptive interference suppression in CDMA systems. The adaptive Parallel-Residue-Compensation architecture leads to significant performance gain over the conventional interference cancellation algorithms. The multi-code commonality is explored to avoid the direct Interference Cancellation (IC), which reduces the IC complexity from OðK 2 NÞ to OðKNÞ. The physical meaning of the complete versus weighted IC is applied to clip the weights above a certain threshold so as to reduce the VLSI circuit activity rate. Novel scalable SoC architectures based on simple combinational logic are proposed to eliminate dedicated multipliers with at least 10Â saving in hardware resource. A Catapult C High Level Synthesis methodology is apply to explore the VLSI design space extensively and achieve at least 4Â speedup. Multi-stage Convergence-Masking-Vector combined with clock gating is proposed to reduce the VLSI dynamic power consumption by up to 90%:

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“…In addition to simulation, emulation has become a standard way of functional verification [5], [6], [8], [9], [12], [13], [15], [20]. Compared to emulation, simulation is characterized by greater controllability and observability, and a cheaper, easier development framework.…”

Section: Introductionmentioning

confidence: 99%

“…Compared to emulation, simulation is characterized by greater controllability and observability, and a cheaper, easier development framework. Simulation is thus typically used earlier in the design cycle, while emulation is used later to uncover bugs that require extremely long executions that cannot be achieved through simulation [8].…”

Section: Introductionmentioning

confidence: 99%

A transaction-based unified architecture for simulation and emulation

Hassoun

Kudlugi

Pryor

et al. 2005

IEEE Trans. VLSI Syst.

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The availability of millions of transistors on a single chip has allowed the creation of complex on-chip systems. The functional verification of such systems has become a challenge. Simulation run times are increasing, and emulation is now a necessity. Creating separate verification environments for simulation and emulation slows the design cycle and it requires additional human efforts. This paper describes a layered architecture suitable for both simulation and emulation. The architecture uses transactions for communication and synchronization between the driving environment (DE) and the device under test (DUT). Transactions provide synchronization only as needed and cycle and event-based synchronization common in emulators. The result is more efficient development of the DE and 100% portability when moving from simulation to emulation. We give an overview of our layered architecture and describe its implementation. Our results show that, by using emulation, the Register-Transfer level (RTL) implementation of an industrial design can be verified in the same amount of time it takes to run a C-based simulation. We also show two orders of magnitude speeds up over simulations of C and RTL through a programming language interface.

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Functional verification of large ASICs

Cited by 39 publications

References 1 publication

Using static analysis for coverage extraction fromemulation/prototyping platforms

Using static analysis for coverage extraction fromemulation/prototyping platforms

A Low Complexity and Low Power SoC Design Architecture for Adaptive MAI Suppression in CDMA Systems

A transaction-based unified architecture for simulation and emulation

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