Fundamental data movement algorithms for reconfigurable meshes

Olariu, Stephan; Schwing, J.L.; Zhang, J.

doi:10.1109/pccc.1992.200593

Cited by 24 publications

(23 citation statements)

References 9 publications

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“…For example, broadcasting on a 1024 processor YUPPIE chip [11] requires only 16 instruction cycles (or 1 cycle for 64 processors). It takes even shorter delay on another chip called GCN, which adopts precharged circuits [14,19]. This confirms the feasibility and potential benefits of the models.…”

Section: Introductionsupporting

confidence: 57%

Fast Inner Product Computation on Short Buses

Lin

Olariu

2001

VLSI Design

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We propose a VLSI inner product processor architecture involving broadcasting only over short buses (containing less than 64 switches). The architecture leads to an efficient algorithm for the inner product computation. Specifically, it takes 13 broadcasts, each over less than 64 switches, plus 2 carry-save additions (t csa ) and 2 carry-lookahead additions (t cla ) to compute the inner product of two arrays of N ¼ 2 9 elements, each consisting of m ¼ 64 bits. Using the same order of VLSI area, our algorithm runs faster than the best known fast inner product algorithm of Smith and Torng ["Design of a fast inner product processor," Proceedings of IEEE 7th Symposium on Computer Arithmetic (1985)], which takes about 28 t csa þ t cla for the computation.

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Section: Introductionsupporting

confidence: 57%

Fast Inner Product Computation on Short Buses

Lin

Olariu

2001

VLSI Design

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“…An equally impressive amount of work has been done on the mesh with reconfigurable buses as well (see e.g., [2,16,17,31,18]). …”

Section: Previous and New Resultsmentioning

confidence: 99%

Mesh connected computers with fixed and reconfigurable buses: Packet routing, sorting, and selection

Rajasekaran

1993

Algorithms—ESA '93

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Mesh connected computers have become attractive models of computing because of their varied special features. In this paper we consider two variations of the mesh model: 1) a mesh with fixed buses, and 2) a mesh with reconfigurable buses. Both these models have been the subject matter of extensive previous research. We solve numerous important problems related to packet routing and sorting on these models. In particular, we provide lower bounds and very nearly matching upper bounds for the following problems on both these models: 1) Routing on a linear array; and 2) k − k routing and k − k sorting on a 2D mesh for any k ≥ 12. We provide an improved algorithm for 1 − 1 routing and a matching sorting algorithm. In addition we present greedy algorithms for 1 − 1 routing, k − k routing, and k − k sorting that are better on average and supply matching lower bounds. We also show that sorting can be performed * This research was supported in part by an NSF Research Initiation Award CCR-92-09260. Preliminary versions of some of the results in this paper were presented in the First Annual European Symposium on Algorithms, 1993. 1 in logarithmic time on a mesh with fixed buses. Most of our algorithms have considerably better time bounds than known algorithms for the same problems.

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“…To begin, given a binary sequence b 1 , b 2 , ..., b n the prefix sum problem involves computing all the sums [22] proved the following result. Our sorting algorithm relies, in part, on the following result proved in Olariu et al [22] and also very easy to obtain from scratch.…”

Section: The Computation Modelmentioning

confidence: 99%

“…The mesh-connected architecture has emerged as one stage for a very powerful computing environment [21].…”

Section: Introductionmentioning

confidence: 99%

“…The reconfigurable mesh combines two desirable features of massively parallel architectures, namely, nearly constant diameter and a dynamically reconfigurable bus system. It is not surprising, therefore, that the sorting problem has received a great deal of attention in the context of reconfigurable architectures [4,7,9,11,13,16,17,19,20,22,23,27,29]. In an early paper, Wang et al [29] proposed a constant-time sorting algorithm on a three-dimensional reconfigurable mesh, using O(n 3 ) processors.…”

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confidence: 99%

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